Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9741680 | Wire bond through-via structure and method | Randy Bindrup, W. Eric Boyd, John Leon, James Yamaguchi | 2017-08-22 |
| 9431275 | Wire bond through-via structure and method | Randy Bindrup, W. Eric Boyd, John Leon, James Yamaguchi | 2016-08-30 |
| 7786562 | Stackable semiconductor chip layer comprising prefabricated trench interconnect vias | Volkan Ozguz, James Yamaguchi, W. Eric Boyd, Douglas Albert, Andrew Camien | 2010-08-31 |
| 7239012 | Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers | James Yamaguchi | 2007-07-03 |
| 7127807 | Process of manufacturing multilayer modules | James Yamaguchi, Volkan Ozguz, Andrew Camien | 2006-10-31 |
| 6797537 | Method of making stackable layers containing encapsulated integrated circuit chips with one or more overlaying interconnect layers | James Yamaguchi | 2004-09-28 |
| 6784547 | Stackable layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers | James Yamaguchi | 2004-08-31 |
| 6734370 | Multilayer modules with flexible substrates | James Yamaguchi, Volkan Ozguz, Andrew Camien | 2004-05-11 |
| 6717061 | Stacking of multilayer modules | James Yamaguchi, Volkan Ozguz, Andrew Camien | 2004-04-06 |
| 6560109 | Stack of multilayer modules with heat-focusing metal layer | James Yamaguchi, Volkan Ozguz, Andrew Camien | 2003-05-06 |
| 5635010 | Dry adhesive joining of layers of electronic devices | David Reinker, Paul Wojtuszewski | 1997-06-03 |
| 5406701 | Fabrication of dense parallel solder bump connections | David Reinker, Joseph A. Minahan | 1995-04-18 |
| 5279991 | Method for fabricating stacks of IC chips by segmenting a larger stack | Joseph A. Minahan | 1994-01-18 |
| 5091288 | Method of forming detector array contact bumps for improved lift off of excess metal | Pierino I. Zappella, William R. Fewer, Eugene J. Babcock | 1992-02-25 |