Issued Patents All Time
Showing 25 most recent of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340304 | Partial sum management and reconfigurable systolic flow architectures for in-memory computation | Mustafa Badaroglu | 2025-06-24 |
| 12074109 | Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methods | Mustafa Badaroglu | 2024-08-27 |
| 12019905 | Digital compute in memory | Mustafa Badaroglu | 2024-06-25 |
| 11790241 | Systems and methods for modifying neural networks for binary processing applications | Matthias REISSER, Saurabh Kedar PITRE, Xiaochun Zhu, Edward Harrison Teague, Max Welling | 2023-10-17 |
| 11631455 | Compute-in-memory bitcell with capacitively-coupled write operation | Seyed Arash Mirhaj, Xiaonan Chen, Ankit Srivastava, Sameer Wadhwa | 2023-04-18 |
| 11626156 | Compute-in-memory (CIM) bit cell circuits each disposed in an orientation of a cim bit cell circuit layout including a read word line (RWL) circuit in a cim bit cell array circuit | Xiaonan Chen | 2023-04-11 |
| 11581037 | Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column | Xiaonan Chen, Yandong Gao, Mustafa Badaroglu | 2023-02-14 |
| 11562212 | Performing XNOR equivalent operations by adjusting column thresholds of a compute-in-memory array | Edward Harrison Teague, Max Welling | 2023-01-24 |
| 11562205 | Parallel processing of a convolutional layer of a neural network with compute-in-memory array | Ye Lu | 2023-01-24 |
| 11551759 | Voltage offset for compute-in-memory architecture | Edward Harrison Teague, Max Welling | 2023-01-10 |
| 11500960 | Memory cell for dot product operation in compute-in-memory chip | Ye Lu, Yandong Gao, Xiaochun Zhu, Xia Li | 2022-11-15 |
| 11494629 | Charge-sharing compute-in-memory system | Xia Li, Xiaochun Zhu | 2022-11-08 |
| 11487507 | Multi-bit compute-in-memory (CIM) arrays employing bit cell circuits optimized for accuracy and power efficiency | Ye Lu, Periannan Chidambaram | 2022-11-01 |
| 11474786 | Fast digital multiply-accumulate (MAC) by fast digital multiplication circuit | Xia Li, Periannan Chidambaram | 2022-10-18 |
| 11340867 | Compute-in-memory (CIM) binary multiplier | Xia Li, Periannan Chidambaram | 2022-05-24 |
| 10964380 | Integrated device comprising memory bitcells comprising shared preload line and shared activation line | Yandong Gao, Xia Li, Ye Lu, Xiaochun Zhu, Xiaonan Chen | 2021-03-30 |
| 10964356 | Compute-in-memory bit cell | Xia Li, Ye Lu, Yandong Gao | 2021-03-30 |
| 10777259 | Static random-access memory (SRAM) for in-memory computing | Xiaochun Zhu | 2020-09-15 |
| 10290352 | System, apparatus, and method of programming a one-time programmable memory circuit having dual programming regions | Xia Li, Xiao Lu, Xiaonan Chen | 2019-05-14 |
| 10194529 | Partial metal fill for preventing extreme-low-k dielectric delamination | Guoqing Chen | 2019-01-29 |
| 10141317 | Metal layers for a three-port bit cell | Niladri Narayan Mojumder, Ritu Chaba, Ping-Lin Liu, Stanley Seungchul Song, Choh Fei Yeap | 2018-11-27 |
| 10037795 | Seven-transistor static random-access memory bitcell with reduced read disturbance | Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Choh Fei Yeap | 2018-07-31 |
| 9941154 | Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device | Stanley Seungchul Song, Choh Fei Yeap, John Jianhong Zhu | 2018-04-10 |
| 9876123 | Non-volatile one-time programmable memory device | Xia Li, Jeffrey Junhao Xu, Xiao Lu, Bin Yang, Jun Yuan +1 more | 2018-01-23 |
| 9876017 | Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells | Niladri Narayan Mojumder, Stanley Seungchul Song, Kern Rim, Choh Fei Yeap | 2018-01-23 |