TJ

Talal K. Jaber

IN Intel: 6 patents #6,151 of 30,777Top 20%
IBM: 5 patents #18,733 of 70,183Top 30%
Overall (All Time): #467,179 of 4,157,543Top 15%
11
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8321730 Scan architecture and design methodology yielding significant reduction in scan area and power overhead David M. Wu 2012-11-27
7734972 Common test logic for multiple operation modes David M. Wu, Ming Zhang 2010-06-08
7437634 Test scan cells Anil K. Sabbavarapu 2008-10-14
7216274 Flexible scan architecture Srinivas Patil, Larry Edward Thatcher, Chih-Jen Lin, Anil K. Sabbavarapu, David M. Wu +1 more 2007-05-08
7028239 Microprocessor on-chip testing architecture and implementation 2006-04-11
6815977 Scan cell systems and methods Anil K. Sabbavarapu, Grant McFarland, Paven R. Sunkerneni, David M. Wu 2004-11-09
6055658 Apparatus and method for testing high speed components using low speed test apparatus Johnny LeBlanc, Ronald Gene Walther 2000-04-25
6028983 Apparatus and methods for testing a microprocessor chip using dedicated scan strings 2000-02-22
5926487 High performance registers for pulsed logic Terry I. Chappell, Michael Kevin Ciraula, Max Eduardo De Ycaza, Sang Hoo Dhong, Rudolf A. Haring +3 more 1999-07-20
5748012 Methodology to test pulsed logic circuits in pseudo-static mode Michael P. Beakes, Barbara A. Chappell, Terry I. Chappell, Bruce M. Fleischer, Rudolf A. Haring +1 more 1998-05-05
5614838 Reduced power apparatus and method for testing high speed components Steven Schmidt 1997-03-25