Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10642744 | Memory type which is cacheable yet inaccessible by speculative instructions | Darrell D. Boggs, Mike Cornaby, Nick Fortino, Shailender Chaudhry, Denis M. Khartikov +3 more | 2020-05-05 |
| 10324725 | Fault detection in instruction translations | Nathan Tuck, David Dunn, Madhu Swarna | 2019-06-18 |
| 10241810 | Instruction-optimizing processor with branch-count table in hardware | Rupert Brauch, Madhu Swarna, David Dunn, Ben Hertzberg | 2019-03-26 |
| 10146545 | Translation address cache for a microprocessor | Alex Klaiber, Nathan Tuck, David Dunn | 2018-12-04 |
| 10108424 | Profiling code portions to generate translations | Nathan Tuck, Alexander Klaiber, David Dunn, Ben Hertzberg, Rupert Brauch +3 more | 2018-10-23 |
| 9891972 | Lazy runahead operation for a microprocessor | Magnus Ekman, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris +4 more | 2018-02-13 |
| 9880846 | Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries | Nathan Tuck | 2018-01-30 |
| 9875105 | Checkpointed buffer for re-entry from runahead | Guillermo J. Rozas, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot +2 more | 2018-01-23 |
| 9823931 | Queued instruction re-dispatch after runahead | Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt +6 more | 2017-11-21 |
| 9740553 | Managing potentially invalid results during runahead | Bruce Holmer, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris +5 more | 2017-08-22 |
| 9632976 | Lazy runahead operation for a microprocessor | Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt +4 more | 2017-04-25 |
| 9563432 | Dynamic configuration of processing pipeline based on determined type of fetched instruction | Darrell D. Boggs, Shiaoli Mendyke | 2017-02-07 |
| 9552032 | Branch prediction power reduction | Aneesh Aggarwal, Kevin Koschoreck, Paul Wasson | 2017-01-24 |
| 9547358 | Branch prediction power reduction | Aneesh Aggarwal, Paul Wasson | 2017-01-17 |
| 9396117 | Instruction cache power reduction | Aneesh Aggarwal, Kevin Koschoreck | 2016-07-19 |
| 7262621 | Method and apparatus for integrated mixed-signal or analog testing | Aaron J. Caffee, Christopher S. Jones, Robert B. Lefferts, Jeffrey L. Sonntag, Daniel K. Weinlader | 2007-08-28 |
| 7047397 | Method and apparatus to execute an instruction with a semi-fast operation in a staggered ALU | — | 2006-05-16 |
| 6735682 | Apparatus and method for address calculation | Feng Chen, David J. Sager | 2004-05-11 |