Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11217295 | Apparatuses and methods for address detection | Kallol Mazumder, Jason M. Brown, Derek R. May, Jeffrey E. Koelling | 2022-01-04 |
| 10534686 | Apparatuses and methods for address detection | Kallol Mazumder, Jason M. Brown, Derek R. May, Jeffrey E. Koelling | 2020-01-14 |
| 7106637 | Asynchronous interface circuit and method for a pseudo-static memory device | Simon J. Lovett, Cliff Zitlaw, Brian M. Shirley, John F. Schreck | 2006-09-12 |
| 6784367 | Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies | Ernest J. Russell, Bharath Nagabhushanam, Terry R. Lee | 2004-08-31 |
| 6690606 | Asynchronous interface circuit and method for a pseudo-static memory device | Simon J. Lovett, Cliff Zitlaw, Brian M. Shirley, John F. Schreck | 2004-02-10 |
| 6548757 | Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies | Ernest J. Russell, Bharath Nagabhushanam, Terry R. Lee | 2003-04-15 |
| 6219294 | Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories | Brian W. Huber, Mansour Fardad | 2001-04-17 |
| 6088280 | High-speed memory arranged for operating synchronously with a microprocessor | Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more | 2000-07-11 |
| 6069829 | Internal clock multiplication for test time reduction | Yutaka Komai, Daniel B. Penny | 2000-05-30 |
| 6049241 | Clock skew circuit | Brian L. Brown | 2000-04-11 |
| 5982694 | High speed memory arranged for operating synchronously with a microprocessor | Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more | 1999-11-09 |
| 5912854 | Data processing system arranged for operating synchronously with a high speed memory | Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more | 1999-06-15 |
| 5910923 | Memory access circuits for test time reduction | Brian L. Brown, David R. Brown, Daniel B. Penney | 1999-06-08 |
| 5808958 | Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock | Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more | 1998-09-15 |
| 5587954 | Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock | Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more | 1996-12-24 |
| 5557219 | Interface level programmability | Brian L. Brown | 1996-09-17 |
| 5475640 | Method and apparatus for inhibiting a predecoder when selecting a redundant row line | David V. Kersh, III | 1995-12-12 |
| 5390149 | System including a data processor, a synchronous dram, a peripheral device, and a system clock | Wilbur C. Vogley, Anthony M. Balistreri, Karl M. Guttag, Steven D. Krueger, Duy-Loan T. Le +3 more | 1995-02-14 |
| 5347184 | Dual receiver edge-triggered digital signal level detection system | Michael C. Stephens, Jr., Duy-Loan T. Le, Kenneth A. Poteet | 1994-09-13 |
| 5327380 | Method and apparatus for inhibiting a predecoder when selecting a redundant row line | David V. Kersh, III | 1994-07-05 |
| 5203867 | Method for generating power-up pulse | Andrew M. Love | 1993-04-20 |
| 5166554 | Boot-strapped decoder circuit | Chitranjan N. Reddy | 1992-11-24 |
| 5030845 | Power-up pulse generator circuit | Andrew M. Love | 1991-07-09 |
| 5010260 | Integrated circuit furnishing a segmented input circuit | David V. Kersh, III | 1991-04-23 |
| 4969123 | Distributed signal transmission to an integrated circuit array | Jimmie D. Childers | 1990-11-06 |