Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11341401 | Hardware architecture for simulating a neural network of neurons | John V. Arthur, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha | 2022-05-24 |
| 11184221 | Yield tolerance in a neurosynaptic system | John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-11-23 |
| 11049001 | Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network | John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-06-29 |
| 10984307 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2021-04-20 |
| 10839287 | Globally asynchronous and locally synchronous (GALS) neuromorphic network | John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha | 2020-11-17 |
| 10769519 | Converting digital numeric data to spike event data | John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson +4 more | 2020-09-08 |
| 10755165 | Converting spike event data to digital numeric data | John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson +4 more | 2020-08-25 |
| 10713561 | Multiplexing physical neurons to optimize power and area | John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha | 2020-07-14 |
| 10650301 | Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2020-05-12 |
| 10454759 | Yield tolerance in a neurosynaptic system | John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2019-10-22 |
| 10410109 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2019-09-10 |
| 10282658 | Hardware architecture for simulating a neural network of neurons | John V. Arthur, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha | 2019-05-07 |
| 10204118 | Mapping neural dynamics of a neural model on to a coarsely grained look-up table | John V. Arthur, Andrew S. Cassidy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha | 2019-02-12 |
| 10176063 | Faulty core recovery mechanisms for a three-dimensional network on a processor array | John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Paul A. Merolla +1 more | 2019-01-08 |
| 10169700 | Neuromorphic network comprising asynchronous routers and synchronous core circuits | John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha | 2019-01-01 |
| 10102474 | Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network | John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-10-16 |
| 9992057 | Yield tolerance in a neurosynaptic system | John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2018-06-05 |
| 9940302 | Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array | John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2018-04-10 |
| 9886662 | Converting spike event data to digital numeric data | John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson +4 more | 2018-02-06 |
| 9881252 | Converting digital numeric data to spike event data | John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson +4 more | 2018-01-30 |
| 9852006 | Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2017-12-26 |
| 9797946 | Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs | John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2017-10-24 |
| 9792251 | Array of processor core circuits with reversible tiers | John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2017-10-17 |
| 9747545 | Self-timed, event-driven neurosynaptic core controller | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2017-08-29 |
| 9588937 | Array of processor core circuits with reversible tiers | John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson +3 more | 2017-03-07 |