Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9870979 | Double-sided segmented line architecture in 3D integration | John W. Golz, Mark D. Jacunski, Toshiaki Kirihata | 2018-01-16 |
| 9559040 | Double-sided segmented line architecture in 3D integration | John W. Golz, Mark D. Jacunski, Toshiaki Kirihata | 2017-01-31 |
| 9543229 | Combination of TSV and back side wiring in 3D integration | John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel | 2017-01-10 |
| 9536809 | Combination of TSV and back side wiring in 3D integration | John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel | 2017-01-03 |
| 9263454 | Semiconductor structure having buried conductive elements | Emre Alptekin, Kangguo Cheng, Ramachandra Divakaruni, Johnathan E. Faltermeier, Reinaldo Vega | 2016-02-16 |
| 9245892 | Semiconductor structure having buried conductive elements | Emre Alptekin, Kangguo Cheng, Ramachandra Divakaruni, Johnathan E. Faltermeier, Reinaldo Vega | 2016-01-26 |