Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163508 | Supporting multiple memory types in a memory slot | Woojong Han, Mohamed Arafa, Brian S. Morris, Mani N. Prakash, John K. Grooms +3 more | 2018-12-25 |
| 7836259 | Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy | Michael Filippo, Roger D. Isaac | 2010-11-16 |
| 7415597 | Processor with dependence mechanism to predict whether a load is dependent on older store | Michael Filippo | 2008-08-19 |
| 7363470 | System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor | Michael Filippo, Benjamin T. Sander | 2008-04-22 |
| 7321964 | Store-to-load forwarding buffer using indexed lookup | Michael Filippo | 2008-01-22 |
| 7266673 | Speculation pointers to identify data-speculative operations in microprocessor | Michael Filippo, Benjamin T. Sander | 2007-09-04 |
| 7251710 | Cache memory subsystem including a fixed latency R/W pipeline | Roger D. Isaac, Mitchell Alsup, Rama S. Gopal, Michael Filippo | 2007-07-31 |
| 7222226 | System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation | Kevin M. Lepak, Benjamin T. Sander | 2007-05-22 |
| 7165167 | Load store unit with replay mechanism | Michael Filippo, Benjamin T. Sander, Rama S. Gopal | 2007-01-16 |
| 7133969 | System and method for handling exceptional instructions in a trace cache based processor | Mitchell Alsup, Gregory W. Smaus, Brian D. McMinn, Michael Filippo, Benjamin T. Sander | 2006-11-07 |
| 7089400 | Data speculation based on stack-relative addressing patterns | Benjamin T. Sander, Kevin M. Lepak | 2006-08-08 |
| 7043626 | Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming | Brian D. McMinn, Mitchell Alsup | 2006-05-09 |
| 7028166 | System and method for linking speculative results of load operations to register values | — | 2006-04-11 |
| 7024537 | Data speculation based on addressing patterns identifying dual-purpose register | Benjamin T. Sander, Kevin M. Lepak | 2006-04-04 |
| 6957319 | Integrated circuit with multiple microcode ROMs | Brian D. McMinn | 2005-10-18 |
| 6957322 | Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion | — | 2005-10-18 |
| 6944744 | Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor | Ashraf Ahmed, Michael Filippo | 2005-09-13 |
| 6845442 | System and method of using speculative operand sources in order to speculatively bypass load-store operations | Kevin M. Lepak, Benjamin T. Sander | 2005-01-18 |
| 6826704 | Microprocessor employing a performance throttling mechanism for power management | — | 2004-11-30 |
| 6438664 | Microcode patch device and method for patching microcode using match registers and patch routines | Kevin J. McGrath | 2002-08-20 |
| 6298424 | Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation | W. Kurt Lewchuk, Brian D. McMinn | 2001-10-02 |
| 6202139 | Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing | David B. Witt | 2001-03-13 |
| 6175908 | Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte | — | 2001-01-16 |
| 6151662 | Data transaction typing for improved caching and prefetching characteristics | David S. Christie, Brian D. McMinn, Stephan G. Meier | 2000-11-21 |
| 6141745 | Functional bit identifying a prefix byte via a particular state regardless of type of instruction | — | 2000-10-31 |