Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12368095 | Simultaneous filling of variable aspect ratio single damascene contact to gate and trench vias with low resistance barrierless selective metallization | Akm Shaestagir Chowdhury, Debashish Basu, Githin F. Alapatt, Justin Mueller | 2025-07-22 |
| 12051623 | Enhanced grating aligned patterning for EUV direct print processes | Seyedhamed M Barghi, Shyam Benegal KADALI, Marvin Young Paik, Sheng-Po Fang, Leonard P. GULER +1 more | 2024-07-30 |
| 11652045 | Via contact patterning method to increase edge placement error margin | Mohit K. HARAN, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An +6 more | 2023-05-16 |
| 11211324 | Via contact patterning method to increase edge placement error margin | Mohit K. HARAN, Daniel James Bahr, Deepak S. Rao, Marvin Young Paik, Seungdo An +6 more | 2021-12-28 |
| 9748180 | Through-body via liner deposition | Puneesh Puri, Jiho Kang | 2017-08-29 |
| 9716066 | Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias | Kevin J. Lee, Hsiao-Kang Chang, John Muirhead, Adwait Telang, Puneesh Puri +2 more | 2017-07-25 |
| 7977248 | Double patterning with single hard mask | Elliot N. Tan, Michael K. Harper | 2011-07-12 |
| 7112534 | Process for low k dielectric plasma etching with high selectivity to deep uv photoresist | Qiang Fu | 2006-09-26 |