Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12293959 | Through-circuit Vias in interconnect structures | Jian-Hong Lin, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu | 2025-05-06 |
| 12243805 | Through-circuit vias in interconnect structures | Jian-Hong Lin, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu | 2025-03-04 |
| 11955441 | Interconnect structure and forming method thereof | Jian-Hong Lin, Kuo-Yen Liu, Tzu-Li Lee, Yu-Ching Lee, Yih Wang | 2024-04-09 |
| 11616002 | Through-circuit vias in interconnect structures | Jian-Hong Lin, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu | 2023-03-28 |
| 11302654 | Method of fabricating semiconductor device including dummy via anchored to dummy metal layer | Jian-Hong Lin, Kuo-Yen Liu, Tzu-Li Lee, Yu-Ching Lee, Yih Wang | 2022-04-12 |
| 10910267 | Alignment marks in substrate having through-substrate via (TSV) | Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2021-02-02 |
| 10777510 | Semiconductor device including dummy via anchored to dummy metal layer | Jian-Hong Lin, Kuo-Yen Liu, Tzu-Li Lee, Yu-Ching Lee, Yih Wang | 2020-09-15 |
| 10692764 | Alignment marks in substrate having through-substrate via (TSV) | Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2020-06-23 |
| 10431541 | Semiconductor device, layout pattern and method for manufacturing an integrated circuit | Jian-Hong Lin, Hui Yu Lee, Yung-Sheng Huang, Yung-Huei Lee | 2019-10-01 |
| 10163706 | Alignment marks in substrate having through-substrate via (TSV) | Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2018-12-25 |
| 9941159 | Method of manufacturing a semiconductor device | Jian-Hong Lin, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee | 2018-04-10 |
| 9449919 | Semiconductor device, layout design and method for manufacturing a semiconductor device | Jian-Hong Lin, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee | 2016-09-20 |
| 9123643 | Chip-on-wafer structures and methods for forming the same | Jing-Cheng Lin, Shih-Ting Lin | 2015-09-01 |
| 9099515 | Reconfigurable guide pin design for centering wafers having different sizes | Hsin-Yu Chen, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng +1 more | 2015-08-04 |
| 8962481 | Chip-on-wafer structures and methods for forming the same | Jin-Cheng Lin, Shih-Ting Lin | 2015-02-24 |
| 8928159 | Alignment marks in substrate having through-substrate via (TSV) | Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng | 2015-01-06 |
| 8643148 | Chip-on-Wafer structures and methods for forming the same | Jing-Cheng Lin, Shih-Ting Lin | 2014-02-04 |
| 8567837 | Reconfigurable guide pin design for centering wafers having different sizes | Hsin-Yu Chen, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng +1 more | 2013-10-29 |
| 6059161 | Assembly of a power stapler | Arosun Lee | 2000-05-09 |