Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393764 | Thermally coupled aware device placement | Akil Khamisi Sutton, Peter Andrew Smith, William Edward Ansley, John G. Massey | 2025-08-19 |
| 11804828 | Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output | Jieming Qi, Daniel M. Dreps, Eric John Lukes, Carrie E. Cox, Timothy O. Dickson | 2023-10-31 |
| 11775002 | Redundant clock switch | Matthew James Paschal, Daniel M. Dreps, Bruce George Rudolph, James D. Strom | 2023-10-03 |
| 11714449 | High-speed deserializer with programmable and timing robust data slip function | Ze Zhang, Dereje G. Yilma, Chad Andrew Marquart | 2023-08-01 |
| 11662381 | Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers | Nathan Ross Blanchard, Venkat Harish Nammi, Dereje G. Yilma, Chad Andrew Marquart, Jeffrey Kwabena Okyere +4 more | 2023-05-30 |
| 11632103 | High-speed voltage clamp for unterminated transmission lines | Chad Andrew Marquart, Daniel M. Dreps | 2023-04-18 |
| 11606082 | Adjustable phase shifter | Yang You, Chad Andrew Marquart, Tyler Bohlke, Daniel M. Dreps | 2023-03-14 |
| 11558045 | Phase rotator | Yang You, Venkat Harish Nammi, Pier Andrea Francese, Chad Andrew Marquart, Daniel M. Dreps | 2023-01-17 |
| 11528102 | Built-in-self-test and characterization of a high speed serial link receiver | Dereje G. Yilma, Nathan Ross Blanchard, Erik English, Chad Andrew Marquart, Jeffrey Kwabena Okyere +5 more | 2022-12-13 |
| 10958248 | Jitter attenuation buffer structure | Yang You, Chad Andrew Marquart, Jeffrey Kwabena Okyere, Daniel M. Dreps, Sudipto Chakraborty | 2021-03-23 |
| 10826810 | Versatile signal detector circuit using common mode shift with all-pass characteristics | Yang You, Pier Andrea Francese, Daniel M. Dreps, Chad Andrew Marquart | 2020-11-03 |
| 9912324 | Open-loop quadrature clock corrector and generator | Paul W. Coteus, Daniel M. Dreps, Kyu-hyoun Kim | 2018-03-06 |
| 9733305 | Frequency-domain high-speed bus signal integrity compliance model | Wiren D. Becker, Daniel M. Dreps, Jose A. Hejase, Si T. Win | 2017-08-15 |
| 9686053 | Frequency-domain high-speed bus signal integrity compliance model | Wiren D. Becker, Daniel M. Dreps, Jose A. Hejase, Si T. Win | 2017-06-20 |
| 9673941 | Frequency-domain high-speed bus signal integrity compliance model | Wiren D. Becker, Daniel M. Dreps, Jose A. Hejase, Si T. Win | 2017-06-06 |
| 9638750 | Frequency-domain high-speed bus signal integrity compliance model | Wiren D. Becker, Daniel M. Dreps, Jose A. Hejase, Si T. Win | 2017-05-02 |
| 9442512 | Interface clock frequency switching using a computed insertion delay | Paul W. Coteus, Daniel M. Dreps, Hillery C. Hunter, Kyu-hyoun Kim | 2016-09-13 |
| 8824573 | Digital phase detector with zero phase offset | Daniel M. Dreps, Kyu-hyoun Kim | 2014-09-02 |
| 8718216 | Digital phase detector with zero phase offset | Daniel M. Dreps, Kyu-hyoun Kim | 2014-05-06 |
| 8674737 | Clock feathered slew rate control system | Marcel A. Kossel, Michael A. Sorna, Thomas H. Toifl | 2014-03-18 |
| 8543753 | Multi-use physical architecture | Daniel M. Dreps, Kyu-hyoun Kim, Michael A. Sorna | 2013-09-24 |
| 8086977 | Design Structure for switching digital circuit clock net driver without losing clock pulses | Jethro C. Law, Kirk E. Morrow, John C. Schiff | 2011-12-27 |
| 7859318 | Delay line regulation using high-frequency micro-regulators | Daniel M. Dreps, Daniel J. Friedman, Seongwon Kim, Hector Saenz | 2010-12-28 |
| 7821300 | System and method for converting between CML signal logic families | Dan P. Bernard, John C. Schiff | 2010-10-26 |
| 7773689 | Multimodal memory controllers | Daniel M. Dreps, Dhaval Sejpal | 2010-08-10 |