Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11960426 | Cable pair concurrent servicing | Rajat Rao, Patrick J. Meaney, Michael Jason Cade, Robert J. Sonnelitter, III, Hubert Harrer +3 more | 2024-04-16 |
| 11907074 | Low-latency deserializer having fine granularity and defective-lane compensation | Patrick J. Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan I. Friedman +2 more | 2024-02-20 |
| 11646861 | Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes | Patrick J. Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan I. Friedman +3 more | 2023-05-09 |
| 11609817 | Low latency availability in degraded redundant array of independent memory | Patrick J. Meaney, David D. Cadigan, Lawrence W. Jones | 2023-03-21 |
| 11520659 | Refresh-hiding memory system staggered refresh | Patrick J. Meaney, David D. Cadigan, Christian Jacobi, Lawrence W. Jones, Stephen J. Powell | 2022-12-06 |
| 11449397 | Cache array macro micro-masking | Gregory J. Fredeman, Thomas E. Miller, Arthur J. O'Neill | 2022-09-20 |
| 11200119 | Low latency availability in degraded redundant array of independent memory | Patrick J. Meaney, David D. Cadigan, Lawrence W. Jones | 2021-12-14 |
| 10833707 | Error trapping in memory structures | Arthur J. O'Neill | 2020-11-10 |
| 10684968 | Conditional memory spreading for heterogeneous memory sizes | David D. Cadigan, Thomas J. Dewkett, Patrick J. Meaney, Craig R. Walters | 2020-06-16 |
| 10601448 | Reduced latency error correction decoding | Patrick J. Meaney, Arthur J. O'Neill, Barry M. Trager | 2020-03-24 |
| 10558519 | Power-reduced redundant array of independent memory (RAIM) system | Patrick J. Meaney | 2020-02-11 |
| 10296417 | Reducing uncorrectable errors based on a history of correctable errors | Patrick J. Meaney | 2019-05-21 |
| 10254961 | Dynamic load based memory tag management | Mark R. Hodges | 2019-04-09 |
| 10055287 | Reducing uncorrectable errors based on a history of correctable errors | Patrick J. Meaney | 2018-08-21 |
| 9946595 | Reducing uncorrectable errors based on a history of correctable errors | Patrick J. Meaney | 2018-04-17 |
| 9594646 | Reestablishing synchronization in a memory system | Patrick J. Meaney, Vesselina K. Papazova, John Steven Dodson | 2017-03-14 |
| 9594647 | Synchronization and order detection in a memory system | Patrick J. Meaney, Eric E. Retter, John Steven Dodson, Gary A. Van Huben, Brad W. Michael +1 more | 2017-03-14 |
| 9563548 | Error injection and error counting during memory scrubbing operations | Lawrence D. Curley, Patrick J. Meaney | 2017-02-07 |
| 9535778 | Reestablishing synchronization in a memory system | Patrick J. Meaney, Vesselina K. Papazova, John Steven Dodson | 2017-01-03 |
| 9495231 | Reestablishing synchronization in a memory system | Patrick J. Meaney, Vesselina K. Papazova, John Steven Dodson | 2016-11-15 |
| 9495254 | Synchronization and order detection in a memory system | Patrick J. Meaney, Eric E. Retter, John Steven Dodson, Gary A. Van Huben, Brad W. Michael +1 more | 2016-11-15 |
| 9459997 | Error injection and error counting during memory scrubbing operations | Lawrence D. Curley, Patrick J. Meaney | 2016-10-04 |
| 9430418 | Synchronization and order detection in a memory system | Patrick J. Meaney, Eric E. Retter, John Steven Dodson, Gary A. Van Huben, Brad W. Michael +1 more | 2016-08-30 |
| 9318171 | Dual asynchronous and synchronous memory system | Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson +4 more | 2016-04-19 |
| 9146864 | Address mapping including generic bits for universal addressing independent of memory type | Eric E. Retter, Patrick J. Meaney, Vesselina K. Papazova, Mark R. Hodges | 2015-09-29 |