Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10707175 | Asymmetric overlay mark for overlay measurement | Wei Zhao, Minghao Tang, Rui Chen, Dongyue Yang, Haiting Wang +1 more | 2020-07-07 |
| 10475890 | Scaled memory structures or other logic devices with middle of the line cuts | Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu +3 more | 2019-11-12 |
| 9397004 | Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings | Guillaume Bouche, Scott Beasor, Andy Wei, Deniz E. Civay | 2016-07-19 |
| 9136175 | Methods for fabricating integrated circuits | Andy Wei, Peter Baars | 2015-09-15 |
| 8927407 | Method of forming self-aligned contacts for a semiconductor device | Peter Baars, Andy Wei, Martin Mazur | 2015-01-06 |
| 8614123 | Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures | Andy Wei, Peter Baars | 2013-12-24 |
| 8592302 | Patterning method for fabrication of a semiconductor device | Peter Baars | 2013-11-26 |
| 8557666 | Methods for fabricating integrated circuits | Andy Wei, Peter Baars | 2013-10-15 |
| 8071485 | Method of semiconductor manufacturing for small features | Doug H. Lee | 2011-12-06 |
| 7601641 | Two step optical planarizing layer etch | Christopher M. Prindle, Sven Beyer | 2009-10-13 |