Issued Patents All Time
Showing 25 most recent of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9070791 | Tunable capacitor | Corey K. Barrows, Joseph A. Iadanza, Edward J. Nowak, Mark S. Styduhar | 2015-06-30 |
| 8519772 | Alternate power gating enablement | Albert M. Chu, Daryl M. Seitzer, Rohit Shetty | 2013-08-27 |
| 8015526 | Static timing slacks analysis and modification | Thomas Chadwick, Margaret R. Charlebois, David J. Hathaway, Jason Rotella, Ivan L. Wemple | 2011-09-06 |
| 7821053 | Tunable capacitor | Corey K. Barrows, Joseph A. Iadanza, Edward J. Nowak, Mark S. Styduhar | 2010-10-26 |
| 7696811 | Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications | Corey K. Barrows, Douglas W. Kemerer, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar +1 more | 2010-04-13 |
| 7671666 | Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications | Corey K. Barrows, Douglas W. Kemerer, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar +1 more | 2010-03-02 |
| 7619398 | Programmable on-chip sense line | Corey K. Barrows, Douglas W. Kemerer, Peter A. Twombly | 2009-11-17 |
| 7579897 | Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices | Kenneth J. Goodnow, Joseph A. Iadanza, Edward J. Nowak | 2009-08-25 |
| 7474124 | Electronic circuit for maintaining and controlling data bus state | Bret Roberts Dale, Darin James Daudelin, Todd Fisher | 2009-01-06 |
| 7475366 | Integrated circuit design closure method for selective voltage binning | Mark W. Kuemerle, Susan K. Lichtensteiger, Ivan L. Wemple | 2009-01-06 |
| 7459958 | Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications | Corey K. Barrows, Douglas W. Kemerer, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar +1 more | 2008-12-02 |
| 7454305 | Method and apparatus for storing circuit calibration information | Anthony R. Bonaccio, Allen Haar, Joseph A. Iadanza, Ivan L. Wemple | 2008-11-18 |
| 7404163 | Static timing slacks analysis and modification | Thomas Chadwick, Margaret R. Charlebois, David J. Hathaway, Jason Rotella, Ivan L. Wemple | 2008-07-22 |
| 7348657 | Electrostatic discharge protection networks for triple well semiconductor devices | James P. Pequignot, Jeffrey H. Sloan, Steven H. Voldman | 2008-03-25 |
| 7307467 | Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices | Kenneth J. Goodnow, Joseph A. Iadanza, Edward J. Nowak | 2007-12-11 |
| 7266789 | Method and apparatus of optimizing the IO collar of a peripheral image | Wai Ling Chung-Maloney, Haruo Ito | 2007-09-04 |
| 7222248 | Method of switching voltage islands in integrated circuits when a grid voltage at a reference location is within a specified range | Rafael Blanco, John M. Cohn, Kenneth J. Goodnow, Sebastian T. Ventrone | 2007-05-22 |
| 7194707 | Method and apparatus for depopulating peripheral input/output cells | Wai Ling Chung-Maloney, Steven J. Urish | 2007-03-20 |
| 7142991 | Voltage dependent parameter analysis | David J. Hathaway, Ivan L. Wemple | 2006-11-28 |
| 7138701 | Electrostatic discharge protection networks for triple well semiconductor devices | James P. Pequignot, Jeffrey H. Sloan, Steven H. Voldman | 2006-11-21 |
| 7131074 | Nested voltage island architecture | Thomas R. Bednar, Scott Whitney Gould, David E. Lackey, Paul S. Zuchowski | 2006-10-31 |
| 7107469 | Power down processing islands | Rafael Blanco, John M. Cohn, Kenneth J. Goodnow, Sebastian T. Ventrone | 2006-09-12 |
| 7088131 | System and method for power gating | Charles H. Windisch, Jr. | 2006-08-08 |
| 6927614 | High performance state saving circuit | Steven F. Oakland | 2005-08-09 |
| 6891207 | Electrostatic discharge protection networks for triple well semiconductor devices | James P. Pequignot, Jeffrey H. Sloan, Steven H. Voldman | 2005-05-10 |