| 6707142 |
Package stacked semiconductor device having pin linking means |
Wan Choi |
2004-03-16 |
| 6319828 |
Method for manufacturing a chip scale package having copper traces selectively plated with gold |
Hai-Jeong Sohn, Dong-Ho Lee |
2001-11-20 |
| 6229205 |
Semiconductor device package having twice-bent tie bar and small die pad |
Kyung Seob Kim |
2001-05-08 |
| 6087722 |
Multi-chip package |
Kwan-Jai Lee, Young Jae Song, Tae-Je Cho, Suk Chang, Chang-Cheol Lee +2 more |
2000-07-11 |
| 6013946 |
Wire bond packages for semiconductor chips and related methods and assemblies |
Kyu Jin Lee, Jae June Kim |
2000-01-11 |
| 5894107 |
Chip-size package (CSP) using a multi-layer laminated lead frame |
Kyu Jin Lee, Wan Gyan Choi, Tae-Gyeong Chung |
1999-04-13 |
| 5811875 |
Lead frames including extended tie-bars, and semiconductor chip packages using same |
Hai-Jeong Sohn, Hyeon J. Jeong |
1998-09-22 |
| 5804874 |
Stacked chip package device employing a plurality of lead on chip type semiconductor chips |
Min Cheol An |
1998-09-08 |
| 5744827 |
Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements |
Min Cheol An, Seung Ho Ahn, Hyeon J. Jeong, Ki-Won Choi |
1998-04-28 |
