Issued Patents All Time
Showing 25 most recent of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11301600 | Methods for generating a contributor-based power abstract for a device | Nagashyamala R. Dhanwada, William W. Dungan, Arun Joseph, Gaurav Mittal, Ricardo H. Nigaglioni | 2022-04-12 |
| 10707951 | Integrated communication and application system for aircraft | — | 2020-07-07 |
| 10460048 | Methods for generating a contributor-based power abstract for a device | Nagashyamala R. Dhanwada, William W. Dungan, Arun Joseph, Gaurav Mittal, Ricardo H. Nigaglioni | 2019-10-29 |
| 10210297 | Optimizing placement of circuit resources using a globally accessible placement memory | Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess | 2019-02-19 |
| 9985843 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, Kerim Kalafala, Ronald D. Rose | 2018-05-29 |
| 9973263 | Integrated communication and application system for aircraft | — | 2018-05-15 |
| 9864824 | System and method for efficient statistical timing analysis of cycle time independent tests | Kerim Kalafala, Stephen G. Shuma, Chandramouli Visweswariah | 2018-01-09 |
| 9852246 | System and method for efficient statistical timing analysis of cycle time independent tests | Kerim Kalafala, Stephen G. Shuma, Chandramouli Visweswariah | 2017-12-26 |
| 9853866 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, Kerim Kalafala, Ronald D. Rose | 2017-12-26 |
| 9836571 | Applying random nets credit in an efficient static timing analysis | Ronald D. Rose | 2017-12-05 |
| 9785737 | Parallel multi-threaded common path pessimism removal in multiple paths | Kerim Kalafala, Vasant Rao, Alexander J. Suess, Vladimir Zolotov | 2017-10-10 |
| 9747400 | Optimizing placement of circuit resources using a globally accessible placement memory | Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess | 2017-08-29 |
| 9703914 | Optimizing placement of circuit resources using a globally accessible placement memory | Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess | 2017-07-11 |
| 9650153 | Integrated communication and application system for aircraft | — | 2017-05-16 |
| 9639654 | Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit | Bijian Chen, Nathaniel D. Hieter, Kerim Kalafala, Jeffrey S. Piaget, Alexander J. Suess | 2017-05-02 |
| 9608868 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, Kerim Kalafala, Ronald D. Rose | 2017-03-28 |
| 9542524 | Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction | James C. Gregerson, Kerim Kalafala, Tsz-Mei Ko, Alex Rubin | 2017-01-10 |
| 9519747 | Dynamic and adaptive timing sensitivity during static timing analysis using look-up table | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett +6 more | 2016-12-13 |
| 9495218 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, Kerim Kalafala, Ronald D. Rose | 2016-11-15 |
| 9436791 | Optimizing placement of circuit resources using a globally accessible placement memory | Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess | 2016-09-06 |
| 9424381 | Contributor-based power modeling of microprocessor components | Nagashyamala R. Dhanwada, Victor Zyuban | 2016-08-23 |
| 9418188 | Optimizing placement of circuit resources using a globally accessible placement memory | Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess | 2016-08-16 |
| 9400864 | System and method for maintaining slack continuity in incremental statistical timing analysis | Jeffrey G. Hemmett, Kerim Kalafala, Debjit Sinha | 2016-07-26 |
| 9378328 | Modeling multi-patterning variability with statistical timing | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz +4 more | 2016-06-28 |
| 9348962 | Hierarchical design of integrated circuits with multi-patterning requirements | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett +3 more | 2016-05-24 |