Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5349229 | Local interconnect for integrated circuits | Fu-Tai Liou | 1994-09-20 |
| 5346860 | Method for fabricating an interconnect structure in an integrated circuit | — | 1994-09-13 |
| 5326724 | Oxide-capped titanium silicide formation | — | 1994-07-05 |
| 5317192 | Semiconductor contact via structure having amorphous silicon side walls | Fusen Chen, Girish Dixit | 1994-05-31 |
| 5313084 | Interconnect structure for an integrated circuit | — | 1994-05-17 |
| 5304504 | Method of forming a gate overlap LDD structure | Ravishankar Sundaresan | 1994-04-19 |
| 5278098 | Method for self-aligned polysilicon contact formation | Chiara Zaccherini, Robert O. Miller, Girish Dixit | 1994-01-11 |
| 5276347 | Gate overlapping LDD structure | Ravishankar Sundaresan | 1994-01-04 |
| 5260229 | Method of forming isolated regions of oxide | Robert Louis Hodges, Frank R. Bryant, Fusen Chen | 1993-11-09 |
| 5246883 | Semiconductor contact via structure and method | Yih-Shung Lin, Lun-Tseng Lu, Fu-Tai Liou, John L. Walters | 1993-09-21 |
| 5173450 | Titanium silicide local interconnect process | — | 1992-12-22 |
| 5166770 | Silicided structures having openings therein | Thomas E. Tang, Cheng-Eng D. Chen | 1992-11-24 |
| 5124280 | Local interconnect for integrated circuits | Fu-Tai Liou | 1992-06-23 |
| 5108951 | Method for forming a metal contact | Fusen Chen, Fu-Tai Liou, Yih-Shung Lin, Girish Dixit | 1992-04-28 |
| 5043778 | Oxide-isolated source/drain transistor | Clarence W. Teng, Thomas E. Tang | 1991-08-27 |
| 5010032 | Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects | Thomas E. Tang, Roger A. Haken, Richard A. Chapman | 1991-04-23 |
| 4975756 | SRAM with local interconnect | Roger A. Haken, Thomas E. Tang, Larry R. Hite | 1990-12-04 |
| 4963502 | Method of making oxide-isolated source/drain transistor | Clarence W. Teng, Thomas E. Tang | 1990-10-16 |
| 4920073 | Selective silicidation process using a titanium nitride protective layer | Thomas E. Tang, James G. Bohlman, Monte A. Douglas | 1990-04-24 |
| 4890141 | CMOS device with both p+ and n+ gates | Thomas E. Tang, Roger A. Haken, Richard A. Chapman | 1989-12-26 |
| 4788160 | Process for formation of shallow silicided junctions | Robert H. Havemann, Roger A. Haken, Thomas E. Tang | 1988-11-29 |
| 4746219 | Local interconnect | Thomas C. Holloway, Thomas E. Tang, Roger A. Haken, David A. Bell | 1988-05-24 |
| 4690730 | Oxide-capped titanium silicide formation | Thomas E. Tang, Roger A. Haken, Thomas C. Holloway, David A. Bell | 1987-09-01 |
| 4676866 | Process to increase tin thickness | Thomas E. Tang, Roger A. Haken, Thomas C. Holloway | 1987-06-30 |
| 4657628 | Process for patterning local interconnects | Thomas C. Holloway, Thomas E. Tang, Roger A. Haken, David A. Bell | 1987-04-14 |