Issued Patents All Time
Showing 51–75 of 98 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6775789 | Method, system and program products for generating sequence values that are unique across operating system images | David A. Elko, Jeffrey M. Nick, Ronald M. Smith, Sr. | 2004-08-10 |
| 6751708 | Method for ensuring that a line is present in an instruction cache | John S. Liptay, Mark A. Check, Mark S. Farrell, Bruce C. Giamei | 2004-06-15 |
| 6671793 | Method and system for managing the result from a translator co-processor in a pipelined processor | Scott Barnett Swaney, Mark S. Farrell, John D. Macdougall, Hans-Juergen Muenster | 2003-12-30 |
| 6662296 | Method and system for testing millicode branch points | Mark S. Farrell, John S. Liptay | 2003-12-09 |
| 6560687 | Method of implementing a translation lookaside buffer with support for a real space control | Aaron Tsai, Chung-Lung K. Shum, Dean G. Bair, Rebecca S. Wisniewski | 2003-05-06 |
| 6490689 | Managing instruction execution in order to accommodate a physical clock value in a clock representation | David A. Elko, Jeffrey M. Nick, Ronald M. Smith, Sr. | 2002-12-03 |
| 6233655 | Method for Quad-word Storing into 2-way interleaved L1 cache | Chung-Lung K. Shum, Wen H. Li | 2001-05-15 |
| 6125444 | Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all | Mark A. Check, John S. Liptay, Timothy J. Slegel, Mark S. Farrell | 2000-09-26 |
| 6119219 | System serialization with early release of individual processor | Dean G. Bair, Mark S. Farrell, Barry W. Krumm, Pak-kin Mak, Jennifer A. Navarro +1 more | 2000-09-12 |
| 6108776 | Globally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computer | Mark A. Check, John S. Liptay, Timothy J. Slegel, Mark S. Farrell | 2000-08-22 |
| 6105126 | Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code | Mark A. Check, Ronald M. Smith, Sr., John S. Liptay, Eric M. Schwarz, Timothy J. Slegel | 2000-08-15 |
| 6105109 | System speed loading of a writable cache code array | Barry W. Krumm, Timothy J. Slegel, Mark S. Farrell, Yuen H. Chan | 2000-08-15 |
| 6088791 | Computer processor system for implementing the ESA/390 STOSM and STNSM instructions without serialization or artificially extending processor execution time | Timothy J. Slegel | 2000-07-11 |
| 6088792 | Avoiding processor serialization after an S/390 SPKA instruction | Timothy J. Slegel | 2000-07-11 |
| 6085313 | Computer processor system for executing RXE format floating point instructions | Mark A. Check, Ronald M. Smith, Sr., John S. Liptay, Eric M. Schwarz, Timothy J. Slegel | 2000-07-04 |
| 6079013 | Multiprocessor serialization with early release of processors | Dean G. Bair, Mark S. Farrell, Barry W. Krumm, Pak-kin Mak, Jennifer A. Navarro +1 more | 2000-06-20 |
| 6067617 | Specialized millicode instructions for packed decimal division | Wen H. Li | 2000-05-23 |
| 6058470 | Specialized millicode instruction for translate and test | Mark S. Farrell | 2000-05-02 |
| 6055624 | Millicode flags with specialized update and branch instructions | Mark S. Farrell, Timothy J. Slegel | 2000-04-25 |
| 6055623 | Specialized millicode instruction for editing functions | Judy S. Johnson | 2000-04-25 |
| 6035392 | Computer with optimizing hardware for conditional hedge fetching into cache storage | John S. Liptay, Mark A. Check, Barry W. Krumm, Jennifer A. Navarro | 2000-03-07 |
| 6026488 | Method for conditional hedge fetching into cache storage | John S. Liptay, Mark A. Check, Barry W. Krumm, Jennifer A. Navarro | 2000-02-15 |
| 5819078 | Addressing extended memory using millicode by concatenating a small millicode address and address extension data | Mark S. Farrell, Barry W. Krumm, Jennifer Serena Almoradie Navarro | 1998-10-06 |
| 5802359 | Mapping processor state into a millicode addressable processor state register array | Mark S. Farrell | 1998-09-01 |
| 5790844 | Millicode load and test access instruction that blocks interrupts in response to access exceptions | Mark S. Farrell, Mark A. Check, John S. Liptay | 1998-08-04 |