Issued Patents All Time
Showing 25 most recent of 194 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9711189 | On-die input reference voltage with self-calibrating duty cycle correction | Bonnie I. Wang, Xiaobao Wang, Yan Chong, Joseph Huang, Khai Nguyen +1 more | 2017-07-18 |
| 9558131 | Integrated circuit with bonding circuits for bonding memory controllers | Jeffrey Erik Schulz, Michael H. Chu | 2017-01-31 |
| 9504156 | Distribution of return paths for improved impedance control and reduced crosstalk | Gopinath Rangan, Khai Nguyen | 2016-11-22 |
| 9473145 | Programmable high-speed I/O interface | Bonnie I. Wang, Joseph Huang, Khai Nguyen, Philip Pan | 2016-10-18 |
| 9208109 | Memory controllers with dynamic port priority assignment capabilities | Michael H. Chu, Jeffrey Erik Schulz, Ravish Kapasi | 2015-12-08 |
| 9166591 | High speed IO buffer | Foong Tek Chan, Xiabao Wang, Khai Nguyen, Ket Chiew Sia, Boon Jin Ang | 2015-10-20 |
| 9166589 | Multiple data rate interface architecture | Philip Pan, Joseph Huang, Yan Chong, Bonnie I. Wang | 2015-10-20 |
| 9158873 | Circuit design technique for DQS enable/disable calibration | Yan Chong, Joseph Huang, Sean Shau-Tu Lu, Pradeep Nagarajan | 2015-10-13 |
| 9111603 | Systems and methods for memory controller reference voltage calibration | Xiaobao Wang, Joseph Huang | 2015-08-18 |
| 9099999 | Adjustable drive strength input-output buffer circuitry | Bonnie I. Wang, Joseph Huang, Khai Nguyen, Tony Ngai, Zhe Li +1 more | 2015-08-04 |
| 9048823 | Duty cycle distortion correction circuitry | John Henry Bui, Lay Hock Khoo, Khai Nguyen, Ket Chiew Sia | 2015-06-02 |
| 9032162 | Systems and methods for providing memory controllers with memory access request merging capabilities | Ching-Chi Chang, Ravish Kapasi, Jeffrey Erik Schulz, Michael H. Chu, Caroline Ssu-Min Chen | 2015-05-12 |
| 9001595 | Data strobe enable circuitry | Wilma Waiman Shiao, Warren Nordyke, Khai Nguyen | 2015-04-07 |
| 8854078 | Dynamic termination-impedance control for bidirectional I/O pins | Xiaobao Wang, Bonnie I. Wang, Khai Nguyen | 2014-10-07 |
| 8829948 | Programmable high-speed I/O interface | Bonnie I. Wang, Joseph Huang, Khai Nguyen, Philip Pan | 2014-09-09 |
| 8787097 | Circuit design technique for DQS enable/disable calibration | Yan Chong, Joseph Huang, Sean Shau-Tu Lu, Pradeep Nagarajan | 2014-07-22 |
| 8779754 | Method and apparatus for minimizing skew between signals | Yan Chong, Joseph Huang, Eric Choong-Yin Chang, Peter Boyle, Adam Wright | 2014-07-15 |
| 8680905 | Digital PVT compensation for delay chain | Pradeep Nagarajan, Yan Chong, Sean Shau-Tu Lu, Joseph Huang | 2014-03-25 |
| 8671303 | Write-leveling implementation in programmable logic devices | Yan Chong, Bonnie I. Wang, Joseph Huang, Michael H. M. Chu | 2014-03-11 |
| 8630131 | Data strobe enable circuitry | Wilma Waiman Shiao, Warren Nordyke, Khai Nguyen | 2014-01-14 |
| 8624647 | Duty cycle correction circuit for memory interfaces in integrated circuits | Yan Chong, Joseph Huang, Pradeep Nagarajan | 2014-01-07 |
| 8610462 | Input-output circuit and method of improving input-output signals | Xiaobao Wang, Khai Nguyen, Bonnie I. Wang | 2013-12-17 |
| 8593195 | High performance memory interface circuit architecture | Joseph Huang, Philip Pan, Yan Chong, Andy L. Lee, Brian Johnson | 2013-11-26 |
| 8575957 | Multiple data rate interface architecture | Philip Pan, Joseph Huang, Yan Chong, Bonnie I. Wang | 2013-11-05 |
| 8565034 | Variation compensation circuitry for memory interface | Sean Shau-Tu Lu, Joseph Huang, Yan Chong, Pradeep Nagarajan | 2013-10-22 |