Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7203794 | Destructive-read random access memory system buffered with destructive-read memory cache | Brian L. Ji, Toshiaki Kirihata, Seiji Munetoh | 2007-04-10 |
| 7057866 | System and method for disconnecting a portion of an integrated circuit | Louis L. Hsu, Rajiv V. Joshi, Toshiaki Kirihata, Paul C. Parries | 2006-06-06 |
| 6948028 | Destructive-read random access memory system buffered with destructive-read memory cache | Brian L. Ji, Toshiaki Kirihata, Seiji Munetoh | 2005-09-20 |
| 6801980 | Destructive-read random access memory system buffered with destructive-read memory cache | Brian L. Ji, Toshiaki Kirihata, Seiji Munetoh | 2004-10-05 |
| 6674673 | Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture | Louis L. Hsu, Gregory J. Fredeman, Toshiaki Kirihata, Dale E. Pontius | 2004-01-06 |
| 6674676 | Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture | Louis L. Hsu, Gregory J. Fredeman, Toshiaki Kirihata, Dale E. Pontius | 2004-01-06 |
| 6621294 | Pad system for an integrated circuit or device | Louis L. Hsu, Li-Kong Wang | 2003-09-16 |
| 6445611 | Method and arrangement for preconditioning in a destructive read memory | John A. Fifield, Daniel W. Storaska | 2002-09-03 |
| 6440638 | Method and apparatus for resist planarization | John W. Golz, John Zhu | 2002-08-27 |
| 6404689 | Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline | Toshiaki Kirihata, Sang Hoo Dhong | 2002-06-11 |
| 6238963 | Damascene process for forming ferroelectric capacitors | Bomy Chen | 2001-05-29 |
| 5898706 | Structure and method for reliability stressing of dielectrics | Roger A. Dufresne, Charles W. Griffin, William A. Klaasen, Alvin W. Strong | 1999-04-27 |
| 5587614 | Microplanarization of rough electrodes by thin amorphous layers | Clarence W. Teng | 1996-12-24 |