Issued Patents All Time
Showing 25 most recent of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9639495 | Integrated controller for training memory physical layer interface | Glenn Dearth, Gerry Talbot, Anwar Kashem, Edoardo Prete | 2017-05-02 |
| 9374080 | Method and apparatus for power-up detection for an electrical monitoring circuit | Gerald R. Talbot, Warren Anderson | 2016-06-21 |
| 9274938 | Dynamic RAM Phy interface with configurable power states | Shawn Searles, Nicholas T. Humphries, Richard W. Reeves, Hanwoo Cho, Ronald L. Pettyjohn | 2016-03-01 |
| 8880831 | Method and apparatus to reduce memory read latency | Guhan Krishnan, Jonathan Owen, Hanwoo Cho | 2014-11-04 |
| 8607104 | Memory diagnostics system and method with hardware-based read/write patterns | Hanwoo Cho, Tahsin Askar, Philip E. Madrid, Guhan Krishnan, Shawn Searles +1 more | 2013-12-10 |
| 8373447 | Method and apparatus of alternating service modes of an SOI process circuit | Joseph Kidd, Ryan J. Hensley, James R. Magro, Ronald L. Pettyjohn | 2013-02-12 |
| 8358158 | Method and apparatus for phase selection acceleration | Ryan J. Hensley, Warren Anderson, Joseph Kidd | 2013-01-22 |
| 8356155 | Dynamic RAM Phy interface with configurable power states | Shawn Searles, Nicholas T. Humphries, Richard W. Reeves, Hanwoo Cho, Ronald L. Pettyjohn | 2013-01-15 |
| 8274272 | Programmable delay module testing device and methods thereof | Gerald R. Talbot, Hanwoo Cho | 2012-09-25 |
| 7263628 | Method and apparatus for receiver circuit tuning | Claude Gauthier, Aninda Roy, Pradeep Trivedi | 2007-08-28 |
| 7251305 | Method and apparatus to store delay locked loop biasing parameters | Claude Gauthier, Dean Liu, Pradeep Trivedi | 2007-07-31 |
| 7193447 | Differential sense amplifier latch for high common mode input | Shao-Hsien Liu, Tri Tran | 2007-03-20 |
| 7110461 | Technique to enlarge data eyes in wireline communication systems | Aninda Roy, Claude Gauthier | 2006-09-19 |
| 7109767 | Generating different delay ratios for a strobe delay | Aparna Ramachandran, Dong J. Yoon, Tri Tran, Gajendra Prasad Singh, Claude Gauthier | 2006-09-19 |
| 7107475 | Digital delay locked loop with extended phase capture range | Dong J. Yoon, Tri Tran, Gajendra Prasad Singh, Aparna Ramachandran, Claude Gauthier | 2006-09-12 |
| 7106113 | Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver | Claude Gauthier, Pradeep Trivedi, Dean Liu | 2006-09-12 |
| 7062688 | Updating high speed parallel I/O interfaces based on counters | Claude Gauthier, Aninda Roy, Dean Liu | 2006-06-13 |
| 7062662 | I/O resonance cancellation circuit based on charge-pumped capacitors | Claude Gauthier, Aninda Roy | 2006-06-13 |
| 7043683 | Data transmission update technique in low power modes | Claude Gauthier, Aninda Roy | 2006-05-09 |
| 7043379 | Method for quantifying I/O chip/package resonance | Claude Gauthier, Aninda Roy | 2006-05-09 |
| 7017086 | Round-robin updating for high speed I/O parallel interfaces | Aninda Roy, Claude Gauthier | 2006-03-21 |
| 7013254 | Low-complexity, high accuracy model of a CPU power distribution system | Claude Gauthier | 2006-03-14 |
| 6998887 | Calibration technique for phase locked loop leakage current | Claude Gauthier, Pradeep Trivedi | 2006-02-14 |
| 6975144 | System, method and apparatus for improving sense amplifier performance characteristics using process feedback | Claude Gauthier, Aninda Roy | 2005-12-13 |
| 6975977 | Low-complexity, high accuracy model of a CPU anti-resonance system | Claude Gauthier | 2005-12-13 |