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Processor and data processing method incorporating an instruction pipeline with conditional branch direction prediction for fast access to branch target instructions |
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Shadow registers for least recently used data in cache |
Thomas Chadwick, Robert D. Herzl, Kenneth A. Lauricella |
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Structure for implementing dynamic refresh protocols for DRAM based cache |
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Method and system for implementing dynamic refresh protocols for DRAM based cache |
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2011-02-01 |
| 6857065 |
System and method for system initializating a data processing system by selecting parameters from one of a user-defined input, a serial non-volatile memory and a parallel non-volatile memory |
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Real time invariant behavior cache |
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2000-12-05 |
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Apparatus to guarantee TLB inclusion for store operations |
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Directory look-aside table for a virtual storage system including means for minimizing synonym entries |
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