Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11983538 | Load-store unit dual tags and replays | Robert T. Golla | 2024-05-14 |
| 10489155 | Mixed-width SIMD operations using even/odd register pairs for wide data elements | Eric W. Mahurin | 2019-11-26 |
| 10466967 | System and method for piecewise linear approximation | Deepak Mathew, Yurong Sun, Jianming Zhu, Marc Hoffman | 2019-11-05 |
| 9823928 | FIFO load instruction | Mao Zeng, Lucian Codrescu, Erich James Plondke | 2017-11-21 |
| 9824013 | Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors | Christopher Edward Koob, Lucian Codrescu, Suresh K. Venkumahanti | 2017-11-21 |
| 9678754 | System and method of processing hierarchical very long instruction packets | Lucian Codrescu, Erich James Plondke, Suresh K. Venkumahanti, Charles Joseph Tabony | 2017-06-13 |
| 9639503 | Vector indirect element vertical addressing mode with horizontal permute | David Hoyle, Marc Hoffman | 2017-05-02 |
| 9639356 | Arbitrary size table lookup and permutes with crossbar | Marc Hoffman, Jose Fridman | 2017-05-02 |
| 9632781 | Vector register addressing and functions based on a scalar register data value | Marc Hoffman, Jose Fridman, Lucian Codrescu | 2017-04-25 |
| 9342479 | Systems and methods of data extraction in a vector processor | Jose Fridman, Deepak Mathew, Marc Hoffman, Michael John Lopez | 2016-05-17 |
| 9268571 | Selective coupling of an address line to an element bank of a vector register file | Marc Hoffman, Deepak Mathew | 2016-02-23 |
| 9239799 | Memory management unit directed access to system interfaces | Christopher Edward Koob | 2016-01-19 |
| 9130786 | Device and method for computing a channel estimate | Deepak Mathew, Mao Zeng, Marc Hoffman | 2015-09-08 |
| 9116685 | Table call instruction for frequently called functions | Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Suresh K. Venkumahanti, Evandro Menezes | 2015-08-25 |
| 8990543 | System and method for generating and using predicates within a single instruction packet | Lucian Codrescu, Robert A. Lester, Charles Joseph Tabony, Erich James Plondke, Mao Zeng +1 more | 2015-03-24 |
| 8943293 | Configurable cache and method to configure same | Christopher Edward Koob, Lucian Codrescu, Jian Shen | 2015-01-27 |
| 8868888 | System and method of executing instructions in a multi-stage data processing pipeline | Lucian Codrescu, Suresh K. Venkumahanti | 2014-10-21 |
| 8812516 | Determining top N or bottom N data values and positions | Mao Zeng | 2014-08-19 |
| 8812789 | Systems and methods for cache line replacement | Erich James Plondke, Lucian Codrescu | 2014-08-19 |
| 8787422 | Dual fixed geometry fast fourier transform (FFT) | Marc Hoffman, Mao Zeng | 2014-07-22 |
| 8719503 | Configurable cache and method to configure same | Christopher Edward Koob, Lucian Codrescu, Jian Shen | 2014-05-06 |
| 8688761 | Arithmetic logic and shifting device for use in a processor | Muhammad Ahmed, Sujat Jamil | 2014-04-01 |
| 8601234 | Configurable translation lookaside buffer | Erich James Plondke, Lucian Codrescu, Paul Bassett | 2013-12-03 |
| 8527804 | Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accesses | Jentsung Lin, Eai-hsin A. Kuo, Paul Bassett | 2013-09-03 |
| 8464000 | Systems and methods for cache line replacements | Erich James Plondke, Lucian Codrescu | 2013-06-11 |