Issued Patents All Time
Showing 51–66 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9141426 | Processor having per core and package level P0 determination functionality | Malini K. Bhandaru, Matthew Bace, A Leonard Brown, Ian M. Steiner, Eric J. Dehaemer +1 more | 2015-09-22 |
| 9075614 | Managing power consumption in a multi-core processor | Eric Fetzer, Reid James Riedlinger, Don Soltis, William J. Bowhill, Satish Shrimali +5 more | 2015-07-07 |
| 9069555 | Managing power consumption in a multi-core processor | Eric Fetzer, Reid J. Reidlinger, Don Soltis, William J. Bowhill, Satish Shrimali +5 more | 2015-06-30 |
| 8984313 | Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator | Malini K. Bhandaru, Eric J. Dehaemer, Scott P. Bobholz, Raghunandan Makaram | 2015-03-17 |
| 8914650 | Dynamically adjusting power of non-core processor circuitry including buffer circuitry | Krishnakanth V. Sistla, Dean Mulla, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa +1 more | 2014-12-16 |
| 8700937 | Uncore thermal management | Deep Buch, Subramaniam Maiyuran | 2014-04-15 |
| 8244985 | Store performance in strongly ordered microprocessor architecture | Vladimir Pentkovksi, Ling Cen, Deep Buch, David Zhao | 2012-08-14 |
| 7836229 | Synchronizing control and data paths traversed by a data transaction | Bipin Singh, Binata Bhattacharyya | 2010-11-16 |
| 7831776 | Dynamic allocation of home coherency engine tracker resources in link based computing system | Phanindra Kumar Mannava, Stan Domen | 2010-11-09 |
| 7694161 | Uncore thermal management | Deep Buch, Subramaniam Maiyuran | 2010-04-06 |
| 7600080 | Avoiding deadlocks in a multiprocessor system | Binata Bhattacharyya, Chandra P. Joshi, Chung-Chi Wang, Liang Yin, Phanindra Kumar Mannava | 2009-10-06 |
| 7484045 | Store performance in strongly-ordered microprocessor architecture | Vladimir Pentkovksi, Ling Cen, Deep Buch, David Zhao | 2009-01-27 |
| 7076609 | Cache sharing for a chip multiprocessor or multiprocessing system | Jagannath Keshava | 2006-07-11 |
| 6976131 | Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system | Vladimir Pentkovski, Narayanan Iyer, Jagannath Keshava | 2005-12-13 |
| 6842180 | Opportunistic sharing of graphics resources to enhance CPU performance in an integrated microprocessor | Subramaniam Maiyuran, Jagannath Keshava, Salvador Palanca | 2005-01-11 |
| 6718440 | Memory access latency hiding with hint buffer | Subramaniam Maiyuran, Mohammad Abdallah, Jagannath Keshava | 2004-04-06 |