Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8244985 | Store performance in strongly ordered microprocessor architecture | Vladimir Pentkovksi, Vivek Garg, Deep Buch, David Zhao | 2012-08-14 |
| 7822929 | Two-hop cache coherency protocol | — | 2010-10-26 |
| 7761696 | Quiescing and de-quiescing point-to-point links | Binata Bhattacharyya, Rahul Pal, Binoy BALAN, Baskaran Ganesan | 2010-07-20 |
| 7673090 | Hot plug interface control method and apparatus | Shivnandan Kaushik, James B. Crossland, Mohan J. Kumar, Linda J. Rankin, David J. O'Shea | 2010-03-02 |
| 7600078 | Speculatively performing read transactions | Vishal Moondhra, Tessil Thomas | 2009-10-06 |
| 7484045 | Store performance in strongly-ordered microprocessor architecture | Vladimir Pentkovksi, Vivek Garg, Deep Buch, David Zhao | 2009-01-27 |
| 7471675 | Arrangements facilitating ordered transactions | — | 2008-12-30 |
| 7411969 | Method, system, and apparatus for a credit based flow control in a computer system | — | 2008-08-12 |
| 6226698 | Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO | Louise Yeung | 2001-05-01 |
| 6128691 | Apparatus and method for transporting interrupts from secondary PCI busses to a compatibility PCI bus | Ken C. Haren | 2000-10-03 |
| 5931926 | Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO | Louise Yeung | 1999-08-03 |
| 5721834 | System management mode circuits systems and methods | Robert W. Milhaupt, James Bridgwater | 1998-02-24 |
| 5706445 | System management mode circuits, systems and methods | Robert W. Milhaupt, James Bridgwater | 1998-01-06 |
| 5666497 | Bus quieting circuits, systems and methods | Robert W. Milhaupt, James Bridgwater | 1997-09-09 |