Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12236243 | Apparatuses and methods for speculative execution side channel mitigation | Jason W. Brandt, Deepak Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell +11 more | 2025-02-25 |
| 12229269 | Techniques for restricted deployment of targeted processor firmware updates | Chinmay Ashok, Vasudevan Srinivasan, Atanas K. Iwanow, Martin G. Dixon, Scott J. Cape +4 more | 2025-02-18 |
| 11635965 | Apparatuses and methods for speculative execution side channel mitigation | Jason W. Brandt, Deepak Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell +11 more | 2023-04-25 |
| 11237614 | Multicore processor with a control register storing an indicator that two or more cores are to operate at independent performance states | Malini K. Bhandaru, Eric J. Dehaemer, Raghunandan Makaram, Vivek Garg | 2022-02-01 |
| 11218322 | System and method for reconfiguring and deploying soft stock-keeping units | Sergiu D. Ghetie, Neeraj Upasani, Chukwunenye S. Nnebe, Won Lee, SHAILA R. MURTY +5 more | 2022-01-04 |
| 10877549 | Configuring power management functionality in a processor | Malini K. Bhandaru, Eric J. Dehaemer, Raghunandan Makaram, Vivek Garg | 2020-12-29 |
| 10203741 | Configuring power management functionality in a processor | Malini K. Bhandaru, Eric J. Dehaemer, Raghunandan Makaram, Vivek Garg | 2019-02-12 |
| 10191532 | Configuring power management functionality in a processor | Malini K. Bhandaru, Eric J. Dehaemer, Raghunandan Makaram, Vivek Garg | 2019-01-29 |
| 9760155 | Configuring power management functionality in a processor | Malini K. Bhandaru, Eric J. Dehaemer, Raghunandan Makaram, Vivek Garg | 2017-09-12 |
| 9436254 | Method and apparatus for per core performance states | Malini K. Bhandaru, Eric J. Dehaemer, Samuel Ho, Chris Poirier | 2016-09-06 |
| 9323316 | Dynamically controlling interconnect frequency in a processor | Malini K. Bhandaru, Ankush Varma, James Vash, Monica C. Wong-Chan, Eric J. Dehaemer +1 more | 2016-04-26 |
| 9235244 | Configuring power management functionality in a processor | Malini K. Bhandaru, Eric J. Dehaemer, Raghunandan Makaram, Vivek Garg | 2016-01-12 |
| 9141426 | Processor having per core and package level P0 determination functionality | Malini K. Bhandaru, Matthew Bace, A Leonard Brown, Ian M. Steiner, Vivek Garg +1 more | 2015-09-22 |
| 8984313 | Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator | Malini K. Bhandaru, Eric J. Dehaemer, Raghunandan Makaram, Vivek Garg | 2015-03-17 |
| 8301907 | Supporting advanced RAS features in a secured computing system | Mahesh S. Natu, Sham M. Datta, Jeff Wiedemeier, James Vash, Sailesh Kottapalli +1 more | 2012-10-30 |
| 6976155 | Method and apparatus for communicating between processing entities in a multi-processor | Tracy Garrett Drysdale | 2005-12-13 |
| 6779065 | Mechanism for interrupt handling in computer systems that support concurrent execution of multiple threads | Keshav Murty | 2004-08-17 |