Issued Patents All Time
Showing 326–350 of 369 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9361116 | Apparatus and method for low-latency invocation of accelerators | Oren Ben-Kiki, Ilan Pardo, Eliezer Weissmann, Dror Markovich, Yuval Yosef | 2016-06-07 |
| 9354877 | Systems, apparatuses, and methods for performing mask bit compression | Bret L. Toll, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney | 2016-05-31 |
| 9336000 | Instruction execution unit that broadcasts data values at different levels of granularity | Elmoustapha Ould-Ahmed-Vall, Jesus Corbal, Bret L. Toll, Mark J. Charney | 2016-05-10 |
| 9323531 | Systems, apparatuses, and methods for determining a trailing least significant masking bit of a writemask register | Christopher J. Hughes, Mark J. Charney, Jesus Corbal, Milind B. Girkar, Elmoustapha Ould-Ahmedvall +1 more | 2016-04-26 |
| 9244677 | Loop vectorization methods and apparatus | Nalini Vasudevan, Jayashankar Bharadwaj, Christopher J. Hughes, Milind B. Girkar, Mark J. Charney +4 more | 2016-01-26 |
| 9244684 | Limited range vector memory access instructions, processors, methods, and systems | Elmoustapha Ould-Ahmed-Vall | 2016-01-26 |
| 9244687 | Packed data operation mask comparison processors, methods, systems, and instructions | Bret L. Toll, Jesus Corbal San Adrian, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney | 2016-01-26 |
| 9235415 | Permute operations with flexible zero control | Cristina S. Anderson, Mark Buxton, Doron Orenstein | 2016-01-12 |
| 9207942 | Systems, apparatuses,and methods for zeroing of bits in a data element | Elmoustapha Ould-Ahmed-Vall | 2015-12-08 |
| 9122475 | Instruction for shifting bits left with pulling ones into less significant bits | Mikhail Plotnikov, Igor Ermolaev, Andrey Naraikin | 2015-09-01 |
| 9053025 | Apparatus and method for fast failure handling of instructions | Oren Ben-Kiki, Ilan Pardo | 2015-06-09 |
| 8996923 | Apparatus and method to obtain information regarding suppressed faults | Christopher J. Hughes, Jesus Corbal, Mark J. Charney, Milind B. Girkar, Elmoustapha Ould-Ahmed-Vall | 2015-03-31 |
| 8972698 | Vector conflict instructions | Christopher J. Hughes, Mark J. Charney, Yen-Kuang Chen, Jesus Corbal, Andrew T. Forsyth +4 more | 2015-03-03 |
| 8972697 | Gather using index array and finite state machine | Zeev Sperber, Guy Patkin, Stanislav Shwartsman, Shlomo Raikin, Igor Yanover +1 more | 2015-03-03 |
| 8914613 | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits | Zeev Sperber, Benny Eitan, Doron Orenstein | 2014-12-16 |
| 8756403 | Compressed instruction format | Doron Orenstein, Brett L. Toll | 2014-06-17 |
| 8694758 | Mixing instructions with different register sizes | Doron Orenstien, Zeev Sperber, Benny Eitan | 2014-04-08 |
| 8688962 | Gather cache architecture | Shlomo Raikin | 2014-04-01 |
| 8504802 | Compressed instruction format | Doron Orenstien, Bret L. Toll | 2013-08-06 |
| 8447962 | Gathering and scattering multiple data elements | Christopher J. Hughes, Yen-Kuang Chen, Mayank Bomb, Jason W. Brandt, Mark Buxton +13 more | 2013-05-21 |
| 8281109 | Compressed instruction format | Doron Orenstein, Bret L. Toll | 2012-10-02 |
| 8082430 | Representing a plurality of instructions with a fewer number of micro-operations | Ittai Anati, Zeev Sperber, Ido Ouziel, Gregory Pribush, Amir Leibovitz | 2011-12-20 |
| 8078836 | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits | Zeev Sperber, Benny Eitan, Doron Orenstein | 2011-12-13 |
| 7882325 | Method and apparatus for a double width load using a single width load port | Zeev Sperber, Ehud Cohen, Doron Orenstien, Benny Eitan | 2011-02-01 |
| 7451294 | Apparatus and method for two micro-operation flow using source override | Zeev Sperber, Yuval Bustan | 2008-11-11 |