Issued Patents All Time
Showing 51–66 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5682516 | Computer system that maintains system wide cache coherency during deferred communication transactions | Wen-Han Wang, Michael W. Rhodehamel, James M. Brayton, Amit Merchant, Matthew A. Fisch | 1997-10-28 |
| 5659689 | Method and apparatus for transmitting information on a wired-or bus | Samuel E. Calvin | 1997-08-19 |
| 5630075 | Write combining buffer for sequentially addressed partial line operations originating from a single instruction | Mandar Joshi, Andrew F. Glew | 1997-05-13 |
| 5623628 | Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue | James M. Brayton, Michael W. Rhodehamel, Glenn J. Hinton | 1997-04-22 |
| 5615343 | Method and apparatus for performing deferred transactions | Konrad K. Lai, Gurbir Singh, Peter D. MacWilliams, Stephen S. Pawlowski, Michael W. Rhodehamel | 1997-03-25 |
| 5581782 | Computer system with distributed bus arbitration scheme for symmetric and priority agents | Konrad K. Lai, Gurbir Singh, Michael W. Rhodehamel, Matthew A. Fisch | 1996-12-03 |
| 5572703 | Method and apparatus for snoop stretching using signals that convey snoop results | Peter D. MacWilliams, Matthew A. Fisch, Amit Merchant | 1996-11-05 |
| 5572702 | Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency | Michael W. Rhodehamel, Amit Merchant, Matthew A. Fisch, James M. Brayton | 1996-11-05 |
| 5568620 | Method and apparatus for performing bus transactions in a computer system | Konrad K. Lai, Gurbir Singh | 1996-10-22 |
| 5561780 | Method and apparatus for combining uncacheable write data into cache-line-sized write buffers | Andy Glew, Mandar Joshi | 1996-10-01 |
| 5555420 | Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management | P. K. Nizar, David G. Carson | 1996-09-10 |
| 5550988 | Apparatus and method for performing error correction in a multi-processor system | Konrad K. Lai | 1996-08-27 |
| 5551005 | Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches | Wen-Hann Wang, Matthew A. Fisch | 1996-08-27 |
| 5548733 | Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system | Michael W. Rhodehamel, Matthew A. Fisch | 1996-08-20 |
| 5515516 | Initialization mechanism for symmetric arbitration agents | Matthew A. Fisch, Michael W. Rhodehamel | 1996-05-07 |
| 5410710 | Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems | Dave Papworth, P. K. Nizar, David G. Carson | 1995-04-25 |