Issued Patents All Time
Showing 26–50 of 109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10560081 | Method, apparatus, system for centering in a high performance interconnect | Zuoguo Wu, Venkatraman Iyer, Gerald Pasdast, Todd Hinck, David M. Lee +1 more | 2020-02-11 |
| 10552253 | Multichip package link error detection | Venkatraman Iyer, Robert G. Blankenship, Zuoguo Wu | 2020-02-04 |
| 10552357 | Multichip package link | Zuoguo Wu, Debendra Das Sharma, Gerald Pasdast, Ananthan Ayyasamy, Xiaobei Li +2 more | 2020-02-04 |
| 10461805 | Valid lane training | Venkatraman Iyer, Lip Khoon Teh, Zuoguo Wu, Azydee Hamid, Gerald Pasdast | 2019-10-29 |
| 10191877 | Architecture for software defined interconnect switch | David J. Harriman, Manjari Kulkarni, Akshay G. Pethe, Sean O. Stalley, Debendra Das Sharma | 2019-01-29 |
| 10180927 | Device, system and method for communication with heterogeneous physical layers | Akshay G. Pethe, Manjari Kulkarni | 2019-01-15 |
| 10152446 | Link-physical layer interface adapter | Venkatraman Iyer, William R. Halleck, Rahul R. Shah | 2018-12-11 |
| 10146291 | Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints | Robert E. Gough | 2018-12-04 |
| 10139889 | Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints | Robert E. Gough | 2018-11-27 |
| 10073808 | Multichip package link | Zuoguo Wu, Debendra Das Sharma, Gerald Pasdast, Ananthan Ayyasamy, Xiaobei Li +2 more | 2018-09-11 |
| 9952644 | Device power management state transition latency advertisement for faster boot time | Lily P. Looi | 2018-04-24 |
| 9952986 | Power delivery and data transmission using PCIe protocol via USB type-C port | Akshay G. Pethe, David J. Harriman, Abdul Ismail | 2018-04-24 |
| 9952643 | Device power management state transition latency advertisement for faster boot time | Lily P. Looi | 2018-04-24 |
| 9946676 | Multichip package link | Zuoguo Wu, Venkatraman Iyer, Gerald Pasdast, Mark S. Birrittella, Ishwar Agarwal +3 more | 2018-04-17 |
| 9921768 | Low power entry in a shared memory link | Michelle C. Jen, Debendra Das Sharma, Venkatraman Iyer | 2018-03-20 |
| 9830292 | Architected protocol for changing link operating mode | Su Wei Lim | 2017-11-28 |
| 9753529 | Systems, apparatuses, and methods for synchronizing port entry into a low power status | Su Wei Lim | 2017-09-05 |
| 9736276 | Packetized interface for coupling agents | Abhishek Singhal, Jasmin Ajanovic | 2017-08-15 |
| 9710406 | Data transmission using PCIe protocol via USB port | Akshay G. Pethe, David J. Harriman, Abdul Ismail | 2017-07-18 |
| 9692402 | Method, apparatus, system for centering in a high performance interconnect | Zuoguo Wu, Venkatraman Iyer, Gerald Pasdast, Todd Hinck, David M. Lee +1 more | 2017-06-27 |
| 9600433 | System, apparatus and method for integrating non-peripheral component interconnect (PCI) resources into a personal computer system | Arvind Mandhani, Woojong Han, Ken Shoemaker, Madhu Athreya, Shreekant S. Thakkar | 2017-03-21 |
| 9563260 | Systems, apparatuses, and methods for synchronizing port entry into a low power state | Su Wei Lim | 2017-02-07 |
| 9558145 | Method, apparatus and system for measuring latency in a physical unit of a circuit | David J. Harriman, Abdul R. Ismail, Daniel S. Froelich | 2017-01-31 |
| 9547618 | Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) | Ken Shoemaker, Woojong Han, Madhu Athreya, Arvind Mandhani, Shreekant S. Thakkar | 2017-01-17 |
| 9535838 | Atomic operations in PCI express | Jasmin Ajanovic, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark Rosenbluth +13 more | 2017-01-03 |