Issued Patents All Time
Showing 176–200 of 203 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7433992 | Command controlling different operations in different chips | — | 2008-10-07 |
| 7432731 | Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations | Navneet Dour, Hany Fahmy, George Vergis, Christopher E. Cox | 2008-10-07 |
| 7412627 | Method and apparatus for providing debug functionality in a buffered memory channel | Robert M. Ellis, Chris Freeman, John B. Halbert, David J. Zimmerman | 2008-08-12 |
| 7404055 | Memory transfer with early access to critical portion | John B. Halbert, Greg Lemos, Randy B. Osborne | 2008-07-22 |
| 7386765 | Memory device having error checking and correction | Robert M. Ellis, Chris Freeman, John B. Halbert | 2008-06-10 |
| 7353329 | Memory buffer device integrating refresh logic | Robert M. Ellis, Chris Freeman, John B. Halbert, Narendra S. Khandekar, Michael W. Williams | 2008-04-01 |
| 7349233 | Memory device with read data from different banks | John B. Halbert | 2008-03-25 |
| 7350016 | High speed DRAM cache architecture | Herbert Hum, John B. Halbert | 2008-03-25 |
| 7336551 | Semiconductor memory devices and systems, and methods of using having reduced timers and registers | — | 2008-02-26 |
| 7281079 | Method and apparatus to counter mismatched burst lengths | John B. Halbert, Randy B. Osborne | 2007-10-09 |
| 7243205 | Buffered memory module with implicit to explicit memory command expansion | Chris Freeman, Pete D. Vogt, Robert M. Ellis, John B. Halbert, Michael W. Williams | 2007-07-10 |
| 7221609 | Fine granularity DRAM refresh | — | 2007-05-22 |
| 7054999 | High speed DRAM cache architecture | Herbert Hum, John B. Halbert | 2006-05-30 |
| 7050351 | Method and apparatus for multiple row caches per bank | John B. Halbert, Robert M. Ellis, Chris Freeman | 2006-05-23 |
| 6996749 | Method and apparatus for providing debug functionality in a buffered memory channel | Robert M. Ellis, Chris Freeman, John B. Halbert, David J. Zimmerman | 2006-02-07 |
| 6990036 | Method and apparatus for multiple row caches per bank | John B. Halbert, Robert M. Ellis, Chris Freeman | 2006-01-24 |
| 6954822 | Techniques to map cache data to memory arrays | Herbert Hum, John B. Halbert | 2005-10-11 |
| 6785190 | Method for opening pages of memory with a single command | John B. Halbert | 2004-08-31 |
| 6366983 | Method and system for symmetric memory population | — | 2002-04-02 |
| 6269443 | Method and apparatus for automatically selecting CPU clock frequency multiplier | David I. Poisner | 2001-07-31 |
| 6154825 | Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations | Robert N. Murdoch, Michael W. Williams, Narendra S. Khandekar | 2000-11-28 |
| 6112284 | Method and apparatus for latching data from a memory resource at a datapath unit | George R. Hayek, Joe M. Nardone, Aniruddha Kundu | 2000-08-29 |
| 5940848 | Computer system and method for efficiently controlling the opening and closing of pages for an aborted row on page miss cycle | — | 1999-08-17 |
| 5815167 | Method and apparatus for providing concurrent access by a plurality of agents to a shared memory | Manish Muthal, Nilesh V. Shah | 1998-09-29 |
| 5802603 | Method and apparatus for asymmetric/symmetric DRAM detection | Narendra S. Khandekar | 1998-09-01 |