Issued Patents All Time
Showing 51–75 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11023382 | Systems, methods, and apparatuses utilizing CPU storage with a memory reference | Raanan Sade, Mark J. Charney, Joseph Nuzman, Leena K. Puthiyedath, Rinat Rappoport +2 more | 2021-06-01 |
| 11023232 | Control transfer termination instructions of an instruction set architecture (ISA) | Vedvyas Shanbhogue, Uday Savagaonkar, Ravi L. Sahita | 2021-06-01 |
| 11023233 | Methods, apparatus, and instructions for user level thread suspension | Michael Mishaeli, Gilbert Neiger, Asit K. Mallick, Rajesh M. Sankaran, Raghunandan Makaram +3 more | 2021-06-01 |
| 10901940 | Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width | Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant | 2021-01-26 |
| 10877806 | Method and apparatus for securely binding a first processor to a second processor | Daniel Nemiroff | 2020-12-29 |
| 10860709 | Encoded inline capabilities | Michael LeMay, David M. Durham, Michael E. Kounavis, Barry E. Huntley, Vedvyas Shanbhogue +12 more | 2020-12-08 |
| 10785028 | Protection of keys and sensitive data from attack within microprocessor architecture | Milind B. Girkar, Michael LeMay | 2020-09-22 |
| 10740249 | Maintaining processor resources during architectural events | Sanjoy K. Mondal, Richard Uhlig, Gilbert Neiger, Robert T. George | 2020-08-11 |
| 10713177 | Defining virtualized page attributes based on guest page attributes | Gilbert Neiger, Baiju V. Patel, Gur Hildesheim, Ron Rais, Andrew V. Anderson +6 more | 2020-07-14 |
| 10678575 | Instruction-set support for invocation of VMM-configured services without VMM intervention | Gilbert Neiger, Barry E. Huntley, Ravi L. Sahita, Vedvyas Shanbhogue | 2020-06-09 |
| 10671547 | Lightweight trusted tasks | Patrick Koeberl, Steffen Schulz, Vedvyas Shanbhogue, Venkateswara Madduri, Sang W. Kim +1 more | 2020-06-02 |
| 10592244 | Branch type logging in last branch registers | Michael W. Chynoweth, Jonathan D. Combs, Joseph K. Olivas, Beeman C. Strong, Rajshree Chabukswar +5 more | 2020-03-17 |
| 10579492 | Device, system and method for identifying a source of latency in pipeline circuitry | Jonathan D. Combs | 2020-03-03 |
| 10552153 | Efficient range-based memory writeback to improve host to device communication for optimal power and performance | Ren Wang, Chunhui Zhang, Qixiong J. Bian, Bret L. Toll | 2020-02-04 |
| 10545883 | Verification bit for one-way encrypted memory | David M. Durham, Kai Cong, Vedvyas Shanbhogue, Barry E. Huntley, Siddhartha Chhabra +1 more | 2020-01-28 |
| 10503517 | Method for booting a heterogeneous system and presenting a symmetric core view | Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz +19 more | 2019-12-10 |
| 10496573 | Context-sensitive interrupts | Steffen Schulz, Patrick Koeberl, Vedvyas Shanbhogue, Venkateswara Madduri, Sang W. Kim +1 more | 2019-12-03 |
| 10496522 | Virtualizing precise event based sampling | Matthew C. Merten, Beeman C. Strong, Michael W. Chynoweth, Grant G. Zhou, Andreas Kleen +5 more | 2019-12-03 |
| 10445494 | Attack protection for valid gadget control transfers | Vedvyas Shanbhogue, Ravi L. Sahita, Yuriy Bulygin, Xiaoning Li | 2019-10-15 |
| 10430580 | Processor extensions to protect stacks during ring transitions | Vedvyas Shanbhogue, Ravi L. Sahita, Barry E. Huntley, Baiju V. Patel, Deepak Gupta | 2019-10-01 |
| 10394556 | Hardware apparatuses and methods to switch shadow stack pointers | Vedvyas Shanbhogue, Ravi L. Sahita, Barry E. Huntley, Baiju V. Patel, Deepak Gupta | 2019-08-27 |
| 10372197 | User level control of power management policies | Krishnakanth V. Sistla, Jeremy J. Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh +7 more | 2019-08-06 |
| 10365988 | Monitoring performance of a processing device to manage non-precise events | Jonathan D. Combs, Michael W. Chynoweth, Corey D. Gough | 2019-07-30 |
| 10346280 | Monitoring performance of a processor using reloadable performance counters | — | 2019-07-09 |
| 10346167 | Apparatuses and methods for generating a suppressed address trace | Toby Opferman, James B. Crossland, Beeman C. Strong | 2019-07-09 |