Issued Patents All Time
Showing 176–200 of 270 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7443836 | Processing a data packet | Donald F. Hooper, Mark Rosenbluth, Matthew J. Adiletta, Hugh Wilkinson, Robert J. Kushlis | 2008-10-28 |
| 7441245 | Phasing for a multi-threaded network processor | Donald F. Hooper, Mark Rosenbluth, Debra Bernstein, Michael F. Fallon, Sanjeev Kumar Jain | 2008-10-21 |
| 7437724 | Registers for data transfers | Mark Rosenbluth, Debra Bernstein, Matthew J. Adiletta, Hugh Wilkinson | 2008-10-14 |
| 7433307 | Flow control in a network environment | Donald F. Hooper, Myles Wilde, Matthew J. Adiletta | 2008-10-07 |
| 7434221 | Multi-threaded sequenced receive for fast network port stream of packets | Donald F. Hooper, Matthew J. Adiletta | 2008-10-07 |
| 7426215 | Method and apparatus for scheduling packets | David Romano, Sanjeev Kumar Jain, John A. Wishneusky | 2008-09-16 |
| 7424579 | Memory controller for processor having multiple multithreaded programmable units | William R. Wheeler, Bradley A. Burres, Matthew J. Adiletta | 2008-09-09 |
| 7421572 | Branch instruction for processor with branching dependent on a specified bit in a register | Matthew J. Adiletta, William R. Wheeler, Debra Bernstein, Donald F. Hooper | 2008-09-02 |
| 7418540 | Memory controller with command queue look-ahead | Natarajan Rohit, Debra Bernstein, Chang-Ming Lin | 2008-08-26 |
| 7418543 | Processor having content addressable memory with command ordering | Sanjeev Kumar Jain, Debra Bernstein | 2008-08-26 |
| 7418571 | Memory interleaving | Mark Rosenbluth, Matthew J. Adiletta | 2008-08-26 |
| 7412584 | Data alignment micro-architecture systems and methods | Jose Niell, Thomas L. Dmukauskas, Mark Rosenbluth | 2008-08-12 |
| 7376950 | Signal aggregation | Mark Rosenbluth, Debra Bernstein, Myles Wilde | 2008-05-20 |
| 7373514 | High-performance hashing system | Jon Krueger, Wajdi K. Feghali | 2008-05-13 |
| 7366865 | Enqueueing entries in a packet queue referencing packets | Sridhar Lakshmanamurthy, Sanjeev Kumar Jain, Debra Bernstein | 2008-04-29 |
| 7336606 | Circular link list scheduling | David Romano, Donald F. Hooper | 2008-02-26 |
| 7337275 | Free list and ring data structure management | Mark Rosenbluth, Debra Bernstein, John Sweeney, James D. Guilford | 2008-02-26 |
| 7328289 | Communication between processors | Debra Bernstein, Matthew J. Adiletta | 2008-02-05 |
| 7325099 | Method and apparatus to enable DRAM to support low-latency access via vertical caching | Sanjeev Kumar Jain, Mark Rosenbluth, Matthew J. Adiletta | 2008-01-29 |
| 7305500 | Sram controller for parallel processor architecture including a read queue and an order queue for handling requests | Matthew J. Adiletta, William R. Wheeler, James Redfield, Daniel Cutter | 2007-12-04 |
| 7302549 | Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access | Hugh Wilkinson, Matthew J. Adiletta, Mark Rosenbluth, Debra Bernstein, Myles Wilde | 2007-11-27 |
| 7277990 | Method and apparatus providing efficient queue descriptor memory access | Sanjeev Kumar Jain | 2007-10-02 |
| 7269179 | Control mechanisms for enqueue and dequeue operations in a pipelined network processor | Mark Rosenbluth, Debra Bernstein, Matthew J. Adiletta | 2007-09-11 |
| 7246197 | Software controlled content addressable memory in a general purpose execution datapath | Mark Rosenbluth, Debra Bernstein | 2007-07-17 |
| 7240164 | Folding for a multi-threaded network processor | Donald F. Hooper, Hugh Wilkinson, Mark Rosenbluth, Debra Bernstein, Michael F. Fallon +2 more | 2007-07-03 |