Issued Patents All Time
Showing 201–225 of 270 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7225281 | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms | Mark Rosenbluth, Debra Bernstein, Myles Wilde, Matthew J. Adiletta | 2007-05-29 |
| 7216204 | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment | Mark Rosenbluth, Debra Bernstein | 2007-05-08 |
| 7191321 | Microengine for parallel processor architecture | Debra Bernstein, Donald F. Hooper, Matthew J. Adiletta, William R. Wheeler | 2007-03-13 |
| 7191309 | Double shift instruction for micro engine used in multithreaded parallel processor architecture | Matthew Adiletta, William R. Wheeler, Debra Bernstein, Donald F. Hooper | 2007-03-13 |
| 7181573 | Queue array caching in network devices | Mark Rosenbluth, Debra Bernstein | 2007-02-20 |
| 7181594 | Context pipelines | Hugh Wilkinson, Mark Rosenbluth, Matthew J. Adiletta, Debra Bernstein | 2007-02-20 |
| 7181568 | Content addressable memory to identify subtag matches | Mark Rosenbluth | 2007-02-20 |
| 7158964 | Queue management | Mark Rosenbluth, Debra Bernstein, Donald F. Hooper | 2007-01-02 |
| 7149226 | Processing data packets | Mark Rosenbluth, Debra Bernstein | 2006-12-12 |
| 7111296 | Thread signaling in multi-threaded processor | Debra Bernstein, Donald F. Hooper, Matthew J. Adiletta, William R. Wheeler | 2006-09-19 |
| 7107413 | Write queue descriptor count instruction for high speed queuing | Mark Rosenbluth, Debra Bernstein | 2006-09-12 |
| 7082104 | Network device switch | Matthew J. Adiletta, Aaron Gorius, Donald F. Hooper, Douglass Carrigan, Chandra Vora | 2006-07-25 |
| 7043516 | Reduction of add-pipe logic by operand offset shift | Mark D. Matson, John D. Clouser | 2006-05-09 |
| 7023844 | Scalable switching fabric | Matthew J. Adiletta, John Cyr | 2006-04-04 |
| 6983350 | SDRAM controller for parallel processor architecture | William R. Wheeler, Bradley A. Burres, Matthew J. Adiletta | 2006-01-03 |
| 6976095 | Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch | Debra Bernstein, Matthew J. Adiletta | 2005-12-13 |
| 6973550 | Memory access control | Mark Rosenbluth, Debra Bernstein, Richard Guerin | 2005-12-06 |
| 6952824 | Multi-threaded sequenced receive for fast network port stream of packets | Donald F. Hooper, Matthew J. Adiletta | 2005-10-04 |
| 6941438 | Memory interleaving | Mark Rosenbluth | 2005-09-06 |
| 6934951 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section | Hugh Wilkinson, Matthew J. Adiletta, Mark Rosenbluth, Debra Bernstein, Myles Wilde | 2005-08-23 |
| 6895457 | Bus interface with a first-in-first-out memory | Debra Bernstein, Matthew J. Adiletta | 2005-05-17 |
| 6876561 | Scratchpad memory | Debra Bernstein, Matthew J. Adiletta | 2005-04-05 |
| 6868476 | Software controlled content addressable memory in a general purpose execution datapath | Mark Rosenbluth, Debra Bernstein | 2005-03-15 |
| 6823438 | Method for memory allocation and management using push/pop apparatus | Donald F. Hooper, Matthew J. Adiletta, William R. Wheeler | 2004-11-23 |
| 6792488 | Communication between processors | Debra Bernstein, Matthew J. Adiletta | 2004-09-14 |