DB

Dan Baum

IN Intel: 47 patents #694 of 30,777Top 3%
Overall (All Time): #59,611 of 4,157,543Top 2%
47
Patents All Time

Issued Patents All Time

Showing 26–47 of 47 patents

Patent #TitleCo-InventorsDate
11422809 Apparatus and method for multicasting a cache line update using delayed refetch messages Christopher J. Hughes 2022-08-23
11327754 Method and apparatus for approximation using polynomials Jorge Parra, Robert S. Chappell, Michael Espig, Varghese George, Alexander Heinecke +5 more 2022-05-10
11294671 Systems and methods for performing duplicate detection instructions on 2D data Christopher J. Hughes, Michael Espig, Robert Valentine, Bret L. Toll, Elmoustapha Ould-Ahmed-Vall 2022-04-05
11288069 Systems, methods, and apparatuses for tile store Robert Valentine, Menachem Adelman, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll, Milind B. Girkar +9 more 2022-03-29
11288068 Systems, methods, and apparatus for matrix move Robert Valentine, Zeev Sperber, Mark J. Charney, Bret L. Toll, Jesus Corbal +2 more 2022-03-29
11263008 Systems, methods, and apparatuses for tile broadcast Robert Valentine, Zeev Sperber, Mark J. Charney, Bret L. Toll, Jesus Corbal +4 more 2022-03-01
11249761 Systems and methods for performing matrix compress and decompress instructions Michael Espig, James D. Guilford, Wajdi K. Feghali, Raanan Sade, Christopher J. Hughes +7 more 2022-02-15
11200055 Systems, methods, and apparatuses for matrix add, subtract, and multiply Robert Valentine, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll +5 more 2021-12-14
11163565 Systems, methods, and apparatuses for dot production operations Robert Valentine, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll +5 more 2021-11-02
11086623 Systems, methods, and apparatuses for tile matrix multiplication and accumulation Robert Valentine, Zeev Sperber, Mark J. Charney, Bret L. Toll, Rinat Rappoport +7 more 2021-08-10
11080048 Systems, methods, and apparatus for tile configuration Menachem Adelman, Robert Valentine, Zeev Sperber, Mark J. Charney, Bret L. Toll +6 more 2021-08-03
10990396 Systems for performing instructions to quickly convert and use tiles as 1D vectors Bret L. Toll, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Raanan Sade, Robert Valentine +2 more 2021-04-27
10970076 Systems and methods for performing instructions specifying ternary tile logic operations Elmoustapha Ould-Ahmed-Vall, Christopher J. Hughes, Bret L. Toll, Raanan Sade, Robert Valentine +2 more 2021-04-06
10896043 Systems for performing instructions for fast element unpacking into 2-dimensional registers Bret L. Toll, Alexander Heinecke, Christopher J. Hughes, Ronen Zohar, Michael Espig +4 more 2021-01-19
10877756 Systems, methods, and apparatuses for tile diagonal Robert Valentine, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll +2 more 2020-12-29
10838734 Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data Christopher J. Hughes, Bret L. Toll, Alexander Heinecke, Elmoustapha Ould-Ahmed-Vall, Raanan Sade +2 more 2020-11-17
10719323 Systems and methods for performing matrix compress and decompress instructions Michael Espig, James D. Guilford, Wajdi K. Feghali, Raanan Sade, Christopher J. Hughes +7 more 2020-07-21
10664273 Delayed prefetch manager to multicast an updated cache line to processor cores requesting the updated data Christopher J. Hughes 2020-05-26
10509846 Accelerator for processing data Chen Koren 2019-12-17
9026829 Package level power state optimization Eliezer Weissmann, Alon Naveh, Nadav Shulman, Hisham Abu Salah 2015-05-05
8539269 Apparatus and method for high current protection Efraim Rotem, Avinash N. Ananthakrishnan, Doron Rajwan, Kosta Luria, Ronny Korner 2013-09-17
8386807 Power management for processing unit Efraim Rotem, Rajwan Doron, Omer Vikinski, Ronny Korner, Kosta Luria 2013-02-26