Issued Patents All Time
Showing 201–225 of 378 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7859053 | Independently accessed double-gate and tri-gate transistors in same process flow | Peter L. D. Chang | 2010-12-28 |
| 7842537 | Stressed semiconductor using carbon and method for producing the same | Kramadhati V. Ravi | 2010-11-30 |
| 7833889 | Apparatus and methods for improving multi-gate device performance | Ravi Pillarisetty, Titash Rakshit, Jack T. Kavalieros | 2010-11-16 |
| 7825437 | Unity beta ratio tri-gate transistor static random access memory (SRAM) | Ravi Pillarisetty, Suman Datta, Jack T. Kavalieros, Uday Shah | 2010-11-02 |
| 7820513 | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication | Scott A. Hareland, Robert S. Chau, Rafael Rios, Tom Linton, Suman Datta | 2010-10-26 |
| 7821061 | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications | Been-Yih Jin, Jack T. Kavalieros, Robert S. Chau | 2010-10-26 |
| 7820512 | Spacer patterned augmentation of tri-gate transistor gate length | Ravi Pillarisetty, Suman Datta, Jack T. Kavalieros, Uday Shah | 2010-10-26 |
| 7800166 | Recessed channel array transistor (RCAT) structures and method of formation | Ravi Pillarisetty, Gilbert Dewey, Robert S. Chau | 2010-09-21 |
| 7776684 | Increasing the surface area of a memory cell capacitor | Robert S. Chau, Vivek K. De, Suman Datta, Dinesh Somasekhar | 2010-08-17 |
| 7767560 | Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method | Been-Yih Jin, Robert S. Chau, Jack T. Kavalieros | 2010-08-03 |
| 7767519 | One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell | Dinesh Somasekhar, Robert S. Chau | 2010-08-03 |
| 7763943 | Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin | Ravi Pillarisetty, Uday Shah, Titash Rakshit, Jack T. Kavalieros | 2010-07-27 |
| 7759774 | Shielded structures to protect semiconductor devices | David B. Fraser | 2010-07-20 |
| 7745270 | Tri-gate patterning using dual layer gate stack | Uday Shah, Jack T. Kavalieros, Been-Yih Jin | 2010-06-29 |
| 7736956 | Lateral undercut of metal gate in SOI device | Suman Datta, Justin K. Brask, Jack T. Kavalieros, Gilbert Dewey, Mark L. Doczy +1 more | 2010-06-15 |
| 7714397 | Tri-gate transistor device with stress incorporation layer and method of fabrication | Scott A. Hareland, Robert S. Chau, Suman Datta, Been-Yih Jin | 2010-05-11 |
| 7709312 | Methods for inducing strain in non-planar transistor structures | Been-Yih Jin, Uday Shah, Jack T. Kavalieros | 2010-05-04 |
| 7700470 | Selective anisotropic wet etching of workfunction metal for semiconductor devices | Willy Rachmady, Uday Shah, Jack T. Kavalieros | 2010-04-20 |
| 7666727 | Semiconductor device having a laterally modulated gate workfunction and method of fabrication | Scott A. Hareland, Mark L. Doczy, Robert S. Chau | 2010-02-23 |
| 7662689 | Strained transistor integration for CMOS | Boyan Boyanov, Anand S. Murthy, Robert S. Chau | 2010-02-16 |
| 7642610 | Transistor gate electrode having conductor material layer | Anand S. Murthy, Boyan Boyanov, Suman Datta, Been-Yih Jin, Shaofeng Yu +1 more | 2010-01-05 |
| 7642603 | Semiconductor device with reduced fringe capacitance | Suman Datta, Titash Rakshit, Jack T. Kavalieros | 2010-01-05 |
| 7638397 | Method of forming quantum wire gate device | — | 2009-12-29 |
| 7638383 | Faceted catalytic dots for directed nanotube growth | Been-Yih Jin, Robert S. Chau, Marko Radosavljevic | 2009-12-29 |
| 7629643 | Independent n-tips for multi-gate transistors | Ravi Pillarisetty, Suman Datta, Jack T. Kavalieros | 2009-12-08 |