Issued Patents All Time
Showing 101–125 of 199 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10474459 | Apparatus and method of improved permute instructions | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Mark J. Charney, Zeev Sperber +1 more | 2019-11-12 |
| 10459728 | Apparatus and method of improved insert instructions | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Mark J. Charney, Zeev Sperber +1 more | 2019-10-29 |
| 10445092 | Method and apparatus for performing a vector permute with an index and an immediate | Jesus Corbal San Adrian, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark J. Charney, Milind B. Girkar +4 more | 2019-10-15 |
| 10430193 | Packed data element predication processors, methods, systems, and instructions | Buford M. Guy, Ronak Singhal, Mishali Naik | 2019-10-01 |
| 10372455 | Hand held device to perform a bit range isolation instruction | Maxim Loktyukhin, Eric W. Mahurin, Martin G. Dixon, Sean P. Mirkes, David L. Kreitzer +2 more | 2019-08-06 |
| 10372449 | Packed data operation mask concatenation processors, methods, systems, and instructions | Robert Valentine, Jesus Corbal San Andrian, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney | 2019-08-06 |
| 10324718 | Packed rotate processors, methods, systems, and instructions | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal San Andrian, Suleyman Sair, Zeev Sperber +2 more | 2019-06-18 |
| 10282296 | Zeroing a cache line | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +5 more | 2019-05-07 |
| 10261879 | Instruction and logic to test transactional execution status | Ravi Rajwar, Konrad K. Lai, Matthew C. Merten, Martin G. Dixon | 2019-04-16 |
| 10255072 | Architectural register replacement for instructions that use multiple architectural registers | Mark J. Charney, Robert Valentine, Milind B. Girkar, Ashish Jha, Elmoustapha Ould-Ahmed-Vall +2 more | 2019-04-09 |
| 10248524 | Instruction and logic to test transactional execution status | Ravi Rajwar, Konrad K. Lai, Matthew C. Merten, Martin G. Dixon | 2019-04-02 |
| 10241792 | Vector frequency expand instruction | Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Kshitij A. Doshi, Charles R. Yount | 2019-03-26 |
| 10228941 | Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register | Ronak Singhal, Buford M. Guy, Mishali Naik | 2019-03-12 |
| 10223227 | Instruction and logic to test transactional execution status | Ravi Rajwar, Konrad K. Lai, Matthew C. Merten, Martin G. Dixon | 2019-03-05 |
| 10210066 | Instruction and logic to test transactional execution status | Ravi Rajwar, Konrad K. Lai, Matthew C. Merten, Martin G. Dixon | 2019-02-19 |
| 10209986 | Floating point rounding processors, methods, systems, and instructions | Jesus Corbal San Adrian, Cristina S. Anderson, Robert Valentine, Amit Gradstein, Simon Rubanovich +1 more | 2019-02-19 |
| 10210065 | Instruction and logic to test transactional execution status | Ravi Rajwar, Konrad K. Lai, Matthew C. Merten, Martin G. Dixon | 2019-02-19 |
| 10203954 | Instruction and logic to provide conversions between a mask register and a general purpose register or memory | Elmoustapha Ould-Ahmed-Vall, Jesus Corbal, Robert Valentine, Mark J. Charney | 2019-02-12 |
| 10175990 | Gathering and scattering multiple data elements | Christopher J. Hughes, Yen-Kuang Chen, Mayank Bomb, Jason W. Brandt, Mark Buxton +13 more | 2019-01-08 |
| 10170165 | Multiple register memory access instructions, processors, methods, and systems | Glenn J. Hinton, Ronak Singhal | 2019-01-01 |
| 10163468 | Multiple register memory access instructions, processors, methods, and systems | Glenn J. Hinton, Ronak Singhal | 2018-12-25 |
| 10157061 | Instructions for storing in general purpose registers one of two scalar constants based on the contents of vector write masks | Jesus Corbal, Matthew J. Craighead, Andrew T. Forsyth | 2018-12-18 |
| 10153011 | Multiple register memory access instructions, processors, methods, and systems | Glenn J. Hinton, Ronak Singhal | 2018-12-11 |
| 10152401 | Instruction and logic to test transactional execution status | Ravi Rajwar, Konrad K. Lai, Matthew C. Merten, Martin G. Dixon | 2018-12-11 |
| 10153012 | Multiple register memory access instructions, processors, methods, and systems | Glenn J. Hinton, Ronak Singhal | 2018-12-11 |