CY

Charles R. Yount

IN Intel: 22 patents #1,785 of 30,777Top 6%
Overall (All Time): #192,157 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12086594 Vector friendly instruction format and execution thereof Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more 2024-09-10
12032934 Methods and apparatus to perform automatic compiler optimization to enable streaming-store generation for unaligned contiguous write access Rakesh Krishnaiyer, Timothy Creech, Daniel Woodworth, Joshua Cranmer 2024-07-09
11740904 Vector friendly instruction format and execution thereof Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more 2023-08-29
11210096 Vector friendly instruction format and execution thereof Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more 2021-12-28
10795680 Vector friendly instruction format and execution thereof Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more 2020-10-06
10540177 Efficient zero-based decompression Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Kshitij A. Doshi, Bret L. Toll 2020-01-21
10509726 Instructions and logic for load-indices-and-prefetch-scatters operations Indraneil M. Gokhale, Elmoustapha Ould-Ahmed-Vall, Antonio C. Valles 2019-12-17
10318291 Providing vector horizontal compare functionality within a vector register Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Kshitij A. Doshi 2019-06-11
10248488 Fault tolerance and detection by replication of input data and evaluating a packed data execution result Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Kshitij A. Doshi 2019-04-02
10241792 Vector frequency expand instruction Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Kshitij A. Doshi, Bret L. Toll 2019-03-26
10061746 Instruction and logic for a vector format for processing computations 2018-08-28
9971391 Method to assess energy efficiency of HPC system operated with and without power constraints Devadatta V. Bodas, Meenakshi Arunachalam, Ilya Sharapov, Scott Huck, Ramakrishna Huggahalli +4 more 2018-05-15
9928063 Instruction and logic to provide vector horizontal majority voting functionality Elmoustapha Ould-Ahmed-Vall, Kshitij A. Doshi, Suleyman Sair 2018-03-27
9804844 Instruction and logic to provide stride-based vector load-op functionality with mask duplication Elmoustapha Ould-Ahmed-Vall, Kshitij A. Doshi, Suleyman Sair 2017-10-31
9747101 Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked offset-based gathering Elmoustapha Ould-Ahmed-Vall, Kshitij A. Doshi, Suleyman Sair 2017-08-29
9672036 Instruction and logic to provide vector loads with strides and masking functionality Elmoustapha Ould-Ahmed-Vall, Kshitij A. Doshi, Suleyman Sair 2017-06-06
9665371 Providing vector horizontal compare functionality within a vector register Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Kshitij A. Doshi 2017-05-30
9575757 Efficient zero-based decompression Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Kshitij A. Doshi, Bret L. Toll 2017-02-21
9513917 Vector friendly instruction format and execution thereof Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more 2016-12-06
9459866 Vector frequency compress instruction Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Kshitij A. Doshi, Bret L. Toll 2016-10-04
9448794 Instruction and logic to provide vector horizontal majority voting functionality Elmoustapha Ould-Ahmed-Vall, Kshitij A. Doshi, Suleyman Sair 2016-09-20
6931629 Method and apparatus for generation of validation tests Melvyn Goveas 2005-08-16