Issued Patents All Time
Showing 401–425 of 535 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9374414 | Embedding global and collective in a torus network with message class map based tree path selection | Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Philip Heidelberger +4 more | 2016-06-21 |
| 9367384 | Admission control based on the end-to-end availability | Ashish Kundu, Ruchi Mahindru | 2016-06-14 |
| 9361031 | Software indications and hints for coalescing memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2016-06-07 |
| 9361144 | Predictive fetching and decoding for selected return instructions | Michael K. Gschwind | 2016-06-07 |
| 9361146 | Predictive fetching and decoding for selected return instructions | Michael K. Gschwind | 2016-06-07 |
| 9361041 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael +2 more | 2016-06-07 |
| 9354885 | Selective suppression of instruction cache-related directory access | Michael K. Gschwind | 2016-05-31 |
| 9354874 | Scalable decode-time instruction sequence optimization of dependent instructions | Michael K. Gschwind | 2016-05-31 |
| 9354888 | Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching | Michael K. Gschwind | 2016-05-31 |
| 9348643 | Prefetching of discontiguous storage locations as part of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-05-24 |
| 9348523 | Code optimization to enable and disable coalescing of memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum | 2016-05-24 |
| 9348522 | Software indications and hints for coalescing memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2016-05-24 |
| 9342397 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Eric M. Schwarz | 2016-05-17 |
| 9336047 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-05-10 |
| 9336097 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz | 2016-05-10 |
| 9329946 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz | 2016-05-03 |
| 9329869 | Prefix computer instruction for compatibily extending instruction functionality | Michael K. Gschwind | 2016-05-03 |
| 9329850 | Relocation of instructions that use relative addressing | Michael K. Gschwind | 2016-05-03 |
| 9329890 | Managing high-coherence-miss cache lines in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-05-03 |
| 9325703 | Automatic security parameter management and renewal | Ashish Kundu, Ruchi Mahindru, Ajay Mohindra, Mahesh Viswanathan | 2016-04-26 |
| 9323530 | Caching optimized internal instructions in loop buffer | Michael K. Gschwind | 2016-04-26 |
| 9317379 | Using transactional execution for reliability and recovery of transient failures | Michael K. Gschwind | 2016-04-19 |
| 9311228 | Power reduction in server memory system | David M. Daly, Tejas Karkhanis | 2016-04-12 |
| 9311178 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Eric M. Schwarz | 2016-04-12 |
| 9311095 | Using register last use information to perform decode time computer instruction optimization | Michael K. Gschwind | 2016-04-12 |