Issued Patents All Time
Showing 426–450 of 535 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9311093 | Prefix computer instruction for compatibly extending instruction functionality | Michael K. Gschwind | 2016-04-12 |
| 9304935 | Enhancing reliability of transaction execution by using transaction digests | Michael K. Gschwind | 2016-04-05 |
| 9298464 | Instruction merging optimization | Michael K. Gschwind | 2016-03-29 |
| 9298626 | Managing high-conflict cache lines in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-03-29 |
| 9298623 | Identifying high-conflict cache lines in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-03-29 |
| 9292444 | Multi-granular cache management in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-03-22 |
| 9292289 | Enhancing reliability of transaction execution by using transaction digests | Michael K. Gschwind | 2016-03-22 |
| 9292291 | Instruction merging optimization | Michael K. Gschwind | 2016-03-22 |
| 9292337 | Software enabled and disabled coalescing of memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2016-03-22 |
| 9292357 | Software enabled and disabled coalescing of memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2016-03-22 |
| 9286072 | Using register last use infomation to perform decode-time computer instruction optimization | Michael K. Gschwind | 2016-03-15 |
| 9286067 | Method and apparatus for a hierarchical synchronization barrier in a multi-node system | Robert W. Wisniewski | 2016-03-15 |
| 9262343 | Transactional processing based upon run-time conditions | Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz, Chung-Lung K. Shum | 2016-02-16 |
| 9244782 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz | 2016-01-26 |
| 9244781 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz | 2016-01-26 |
| 9229715 | Method and apparatus for efficient inter-thread synchronization for helper threads | Michael K. Gschwind, John Kevin Patrick O'Brien, Zehra N. Sura | 2016-01-05 |
| 9170773 | Mixed precision estimate instruction computing narrow precision result for wide precision inputs | Michael K. Gschwind | 2015-10-27 |
| 9170888 | Methods and apparatus for virtual machine recovery | Richard E. Harper, Kyung D. Ryu | 2015-10-27 |
| 9146774 | Coalescing memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum | 2015-09-29 |
| 9098408 | Ticket consolidation for multi-tiered applications | Ruchi Mahindru | 2015-08-04 |
| 9086974 | Centralized management of high-contention cache lines in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2015-07-21 |
| 9086960 | Ticket consolidation for multi-tiered applications | Ruchi Mahindru | 2015-07-21 |
| 9081501 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +55 more | 2015-07-14 |
| 9069891 | Hardware enabled performance counters with support for operating system context switching | Robert W. Wisniewski | 2015-06-30 |
| 8990514 | Mechanisms for efficient intra-die/intra-chip collective messaging | Amith R. Mamidala, Robert W. Wisniewski | 2015-03-24 |