Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9058861 | Power management SRAM write bit line drive circuit | Derick G. Behrends, Todd A. Christensen, Michael Launsbach | 2015-06-16 |
| 8929116 | Two phase search content addressable memory with power-gated main-search | Igor Arsovski, Michael T. Fragano | 2015-01-06 |
| 8860141 | Layout to minimize FET variation in small dimension photolithography | Derick G. Behrends, Todd A. Christensen, Michael Launsbach, Daniel Mark Nelson | 2014-10-14 |
| 8848414 | Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system | Igor Arsovski, Daniel Dobson | 2014-09-30 |
| 8842487 | Power management domino SRAM bit line discharge circuit | Derick G. Behrends, Todd A. Christensen, Michael Launsbach | 2014-09-23 |
| 8824196 | Single cycle data copy for two-port SRAM | Derick G. Behrends, Todd A. Christensen, Michael Launsbach, Daniel Mark Nelson | 2014-09-02 |
| 8754691 | Memory array pulse width control | Chad A. Adams, Derick G. Behrends | 2014-06-17 |
| 8711606 | Data security for dynamic random access memory using body bias to clear data at power-up | Derick G. Behrends, Todd A. Christensen, Michael Launsbach, Daniel Mark Nelson | 2014-04-29 |
| 8675427 | Implementing RC and coupling delay correction for SRAM | Derick G. Behrends, Todd A. Christensen, Michael Launsbach, Daniel Mark Nelson | 2014-03-18 |
| 8669800 | Implementing power saving self powering down latch structure | Derick G. Behrends, Todd A. Christensen, Michael Launsbach | 2014-03-11 |
| 8578304 | Implementing mulitple mask lithography timing variation mitigation | Derick G. Behrends, Todd A. Christensen, Michael Launsbach | 2013-11-05 |
| 8520429 | Data dependent SRAM write assist | Derick G. Behrends, Todd A. Christensen, Michael Launsbach, Daniel Mark Nelson | 2013-08-27 |
| 8467261 | Implementing smart switched decoupling capacitors to efficiently reduce power supply noise | David P. Paulsen | 2013-06-18 |
| 8467230 | Data security for dynamic random access memory using body bias to clear data at power-up | Derick G. Behrends, Todd A. Christensen, Michael Launsbach, Daniel Mark Nelson | 2013-06-18 |
| 8451668 | Implementing column redundancy steering for memories with wordline repowering | Chad A. Adams | 2013-05-28 |
| 8427894 | Implementing single bit redundancy for dynamic SRAM circuit with any bit decode | Derick G. Behrends, Todd A. Christensen, Peter Thomas Freiburger, Jayson K. Wittrup | 2013-04-23 |
| 8395963 | Data security for dynamic random access memory at power-up | Derick G. Behrends, Todd A. Christensen, Daniel Mark Nelson | 2013-03-12 |
| 8344782 | Method and apparatus to limit circuit delay dependence on voltage for single phase transition | Derick G. Behrends, Todd A. Christensen, Daniel Mark Nelson | 2013-01-01 |
| 8159260 | Delay chain burn-in for increased repeatability of physically unclonable functions | Derick G. Behrends, Todd A. Christensen, Daniel Mark Nelson | 2012-04-17 |
| 8108739 | High-speed testing of integrated devices | Chad A. Adams, Derick G. Behrends, Todd A. Christensen | 2012-01-31 |
| 7971164 | Assessing resources required to complete a VLSI design | Derick G. Behrends, Daniel Mark Nelson, Jesse D. Smith | 2011-06-28 |
| 7924633 | Implementing boosted wordline voltage in memories | Derick G. Behrends, Todd A. Christensen, Daniel Mark Nelson | 2011-04-12 |
| 7911827 | Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels | Derick G. Behrends, Daniel Mark Nelson, Jesse D. Smith | 2011-03-22 |
| 7835176 | Implementing enhanced dual mode SRAM performance screen ring oscillator | Chad A. Adams, Todd A. Christensen, Peter Thomas Freiburger | 2010-11-16 |
| 7788554 | Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation | Chad A. Adams, Derick G. Behrends, Daniel Mark Nelson | 2010-08-31 |