Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9569580 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren | 2017-02-14 |
| 9563736 | Placement aware functional engineering change order extraction | George Antony, Pinaki Chakrabarti, Haoxing Ren | 2017-02-07 |
| 9552451 | Cross-hierarchy interconnect adjustment for power recovery | Christopher J. Berry, Ricardo H. Nigaglioni, Haifeng Qian | 2017-01-24 |
| 9542327 | Selective mirroring in caches for logical volumes | Sumanesh Samanta, Saugata Das Purkayastha, Mohana Rao Goli | 2017-01-10 |
| 9536037 | Circuit placement with electro-migration mitigation | Harald D. Folberth, Dilip Kumar, Sven Peyer, Hameedbasha Shaik | 2017-01-03 |
| 9514265 | Congestion aware layer promotion | Christopher J. Berry, Lakshmi N. Reddy | 2016-12-06 |
| 9501603 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren | 2016-11-22 |
| 9495502 | Congestion aware layer promotion | Christopher J. Berry, Lakshmi N. Reddy | 2016-11-15 |
| 9483601 | Circuit routing based on total negative slack | Harald D. Folberth, Sven Peyer | 2016-11-01 |
| 9471735 | Boundary based power guidance for physical synthesis | Pinaki Chakrabarti, Kaustav Guha, Ricardo H. Nigaglioni | 2016-10-18 |
| 9471741 | Circuit routing based on total negative slack | Harald D. Folberth, Sven Peyer | 2016-10-18 |
| 9443047 | Physical aware technology mapping in synthesis | Pinaki Chakrabarti, Christopher J. Berry, Lakshmi N. Reddy | 2016-09-13 |
| 9443048 | Physical aware technology mapping in synthesis | Christopher J. Berry, Pinaki Chakrabarti, Lakshmi N. Reddy | 2016-09-13 |
| 9443049 | Boundary based power guidance for physical synthesis | Pinaki Chakrabarti, Kaustav Guha, Ricardo H. Nigaglioni | 2016-09-13 |
| 9418190 | Virtual sub-net based routing | Gi-Joon Nam, Sven Peyer, Ronald D. Rose | 2016-08-16 |
| 9412682 | Through-silicon via access device for integrated circuits | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren | 2016-08-09 |
| 9384316 | Path-based congestion reduction in integrated circuit routing | Harald D. Folberth, Sven Peyer | 2016-07-05 |
| 9378151 | System and method of hinted cache data removal | Vineet Agarwal, Durga Prasad Bhattarai | 2016-06-28 |
| 9378326 | Critical region identification | George Antony, Christopher J. Berry, Ricardo H. Nigaglioni, Sridhar H. Rangarajan, Vinay K. Singh | 2016-06-28 |
| 9286428 | Boundary based power guidance for physical synthesis | Pinaki Chakrabarti, Kaustav Guha, Ricardo H. Nigaglioni | 2016-03-15 |
| 9245074 | Boundary based power guidance for physical synthesis | Pinaki Chakrabarti, Kaustav Guha, Ricardo H. Nigaglioni | 2016-01-26 |
| 9245084 | Virtual sub-net based routing | Gi-Joon Nam, Sven Peyer, Ronald D. Rose | 2016-01-26 |
| 9092587 | Congestion estimation techniques at pre-synthesis stage | Dilip Kumar Jha | 2015-07-28 |
| 9053285 | Thermally aware pin assignment and device placement | Randall J. Darden, Shyam Ramji | 2015-06-09 |
| 9009642 | Congestion estimation techniques at pre-synthesis stage | Dilip Kumar Jha | 2015-04-14 |