Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9798847 | Cross-hierarchy interconnect adjustment for power recovery | Christopher J. Berry, Ricardo H. Nigaglioni, Haifeng Qian | 2017-10-24 |
| 9734270 | Control path power adjustment for chip design | Christopher J. Berry, Kaustav Guha, Jose L. Neves, Haifeng Qian | 2017-08-15 |
| 9734268 | Slack redistribution for additional power recovery | Christopher J. Berry, Yiu-Hing Chan, Arjen A. Mets, Charudhattan Nagarajan, Ricardo H. Nigaglioni +1 more | 2017-08-15 |
| 9715572 | Hierarchical wire-pin co-optimization | Christopher J. Berry, Ajith Kumar M. Chandrasekaran, Randall J. Darden, Shyam Ramji | 2017-07-25 |
| 9715565 | Physical aware technology mapping in synthesis | Christopher J. Berry, Pinaki Chakrabarti, Lakshmi N. Reddy | 2017-07-25 |
| 9710585 | Physical aware technology mapping in synthesis | Christopher J. Berry, Pinaki Chakrabarti, Lakshmi N. Reddy | 2017-07-18 |
| 9703924 | Timing constraints formulation for highly replicated design modules | Chithra Ravindranath, Rajashree Srinidhi | 2017-07-11 |
| 9703923 | Timing constraints formulation for highly replicated design modules | Chithra Ravindranath, Rajashree Srinidhi | 2017-07-11 |
| 9703920 | Intra-run design decision process for circuit synthesis | Christopher J. Berry, Lakshmi N. Reddy, Matthew M. Ziegler | 2017-07-11 |
| 9703910 | Control path power adjustment for chip design | Christopher J. Berry, Kaustav Guha, Jose L. Neves, Haifeng Qian | 2017-07-11 |
| 9697322 | Hierarchical wire-pin co-optimization | Christopher J. Berry, Ajith Kumar M. Chandrasekaran, Randall J. Darden, Shyam Ramji | 2017-07-04 |
| 9690900 | Intra-run design decision process for circuit synthesis | Christopher J. Berry, Lakshmi N. Reddy, Matthew M. Ziegler | 2017-06-27 |
| 9684757 | Cross-hierarchy interconnect adjustment for power recovery | Christopher J. Berry, Ricardo H. Nigaglioni, Haifeng Qian | 2017-06-20 |
| 9684751 | Slack redistribution for additional power recovery | Christopher J. Berry, Yiu-Hing Chan, Arjen A. Mets, Charudhattan Nagarajan, Ricardo H. Nigaglioni +1 more | 2017-06-20 |
| 9684759 | De-coupling capacitance placement | Harry Barowski, Joachim Keinert, Thomas Strach | 2017-06-20 |
| 9679099 | De-coupling capacitance placement | Harry Barowski, Joachim Keinert, Thomas Strach | 2017-06-13 |
| 9679101 | Circuit placement with electro-migration mitigation | Harald D. Folberth, Dilip Kumar, Sven Peyer, Hameedbasha Shaik | 2017-06-13 |
| 9672322 | Virtual positive slack in physical synthesis | Christopher J. Berry, Kaustav Guha, Lakshmi N. Reddy | 2017-06-06 |
| 9672321 | Virtual positive slack in physical synthesis | Christopher J. Berry, Kaustav Guha, Lakshmi N. Reddy | 2017-06-06 |
| 9672314 | Logic structure aware circuit routing | Saurabh Gupta, Srujan Nadella, Padmashri Ramalingam | 2017-06-06 |
| 9659140 | Critical region identification | George Antony, Christopher J. Berry, Ricardo H. Nigaglioni, Sridhar H. Rangarajan, Vinay K. Singh | 2017-05-23 |
| 9659135 | Logic structure aware circuit routing | Saurabh Gupta, Srujan Nadella, Padmashri Ramalingam | 2017-05-23 |
| 9633928 | Through-silicon via access device for integrated circuits | Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren | 2017-04-25 |
| 9576102 | Timing constraints formulation for highly replicated design modules | Chithra Ravindranath, Rajashree Srinidhi | 2017-02-21 |
| 9569581 | Logic structure aware circuit routing | Saurabh Gupta, Srujan Nadella, Padmashri Ramalingam | 2017-02-14 |