Issued Patents All Time
Showing 376–400 of 508 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6343344 | System bus directory snooping mechanism for read/castout (RCO) address transaction | John Steven Dodson, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2002-01-29 |
| 6341336 | Cache coherency protocol having tagged state used with cross-bars | John Steven Dodson, Jerry Don Lewis | 2002-01-22 |
| 6338116 | Method and apparatus for a data-less write operation within a cache memory hierarchy for a data processing system | Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Sanjeev Ghai | 2002-01-08 |
| 6338124 | Multiprocessor system bus with system controller explicitly updating snooper LRU information | John Steven Dodson, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2002-01-08 |
| 6336169 | Background kill system bus transaction to optimize coherency transactions on a multiprocessor system bus | James S. Fields, Jr., Guy L. Guthrie | 2002-01-01 |
| 6334172 | Cache coherency protocol with tagged state for modified values | John Steven Dodson, Jerry Don Lewis | 2001-12-25 |
| 6330643 | Cache coherency protocols with global and local posted operations | John Steven Dodson, Jerry Don Lewis | 2001-12-11 |
| 6324617 | Method and system for communicating tags of data access target and castout victim in a single data transfer | John Steven Dodson, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2001-11-27 |
| 6321306 | High performance multiprocessor system with modified-unsolicited cache state | Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2001-11-20 |
| 6321305 | Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data | John Steven Dodson, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2001-11-20 |
| 6314495 | Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations | John Michael Kaiser, Derek E. Williams | 2001-11-06 |
| 6314498 | Multiprocessor system bus transaction for transferring exclusive-deallocate cache state to lower lever cache | Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2001-11-06 |
| 6298416 | Method and apparatus for transmitting control signals within a hierarchial cache memory architecture for a data processing system | Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Sanjeev Ghai, Praveen S. Reddy | 2001-10-02 |
| 6292908 | Method and apparatus for monitoring internal bus signals by using a reduced image of the internal bus | Keenan W. Franz, David B. Shuler, Derek E. Williams | 2001-09-18 |
| 6292872 | Cache coherency protocol having hovering (H) and recent (R) states | John Steven Dodson, Jerry Don Lewis | 2001-09-18 |
| 6286068 | Queued arbitration mechanism for data processing system | John Michael Kaiser | 2001-09-04 |
| 6282615 | Multiprocessor system bus with a data-less castout mechanism | Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Sanjeev Ghai | 2001-08-28 |
| 6279086 | Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position | John Steven Dodson, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2001-08-21 |
| 6275908 | Cache coherency protocol including an HR state | John Steven Dodson, Jerry Don Lewis | 2001-08-14 |
| 6275909 | Multiprocessor system bus with system controller explicitly updating snooper cache state information | John Steven Dodson, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2001-08-14 |
| 6272603 | Cache coherency protocol having hovering (H), recent (R), and tagged (T) states | John Steven Dodson, Jerry Don Lewis | 2001-08-07 |
| 6263407 | Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode | John Steven Dodson, Jerry Don Lewis | 2001-07-17 |
| 6253286 | Apparatus for adjusting a store instruction having memory hierarchy control bits | John S. Dodson, Guy L. Guthrie | 2001-06-26 |
| 6249911 | Optimizing compiler for generating store instructions having memory hierarchy control bits | John S. Dodson, Guy L. Guthrie | 2001-06-19 |
| 6249843 | Store instruction having horizontal memory hierarchy control bits | John S. Dodson, Guy L. Guthrie | 2001-06-19 |