Issued Patents All Time
Showing 401–425 of 508 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6247098 | Cache coherency protocol with selectively implemented tagged state | John Steven Dodson, Jerry Don Lewis | 2001-06-12 |
| 6230242 | Store instruction having vertical memory hierarchy control bits | John S. Dodson, Guy L. Guthrie | 2001-05-08 |
| 6212616 | Even/odd cache directory mechanism | John Steven Dodson, Jerry Don Lewis | 2001-04-03 |
| 6212605 | Eviction override for larx-reserved addresses | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 2001-04-03 |
| 6202131 | Method and apparatus for executing variable delay system bus operations of differing type or character without dead lock using shared buffers | John Michael Kaiser, Derek E. Williams | 2001-03-13 |
| 6195729 | Deallocation with cache update protocol (L2 evictions) | John Steven Dodson, Jerry Don Lewis | 2001-02-27 |
| 6192458 | High performance cache directory addressing scheme for variable cache sizes utilizing associativity | John Steven Dodson, Jerry Don Lewis | 2001-02-20 |
| 6192453 | Method and apparatus for executing unresolvable system bus operations | Derek E. Williams, John Michael Kaiser () | 2001-02-20 |
| 6192451 | Cache coherency protocol for a data processing system including a multi-level memory hierarchy | John Steven Dodson, Jerry Don Lewis | 2001-02-20 |
| 6185658 | Cache with enhanced victim selection using the coherency states of cache lines | John Steven Dodson, Jerry Don Lewis | 2001-02-06 |
| 6182201 | Demand-based issuance of cache operations to a system bus | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 2001-01-30 |
| 6178484 | DCBST with ICBI mechanism to maintain coherency of bifurcated data and instruction caches | John Steven Dodson, Jerry Don Lewis | 2001-01-23 |
| 6178485 | Method and apparatus for executing singly-initiated, singly-sourced variable delay system bus operations of differing character | Derek E. Williams, John Michael Kaiser | 2001-01-23 |
| 6175930 | Demand based sync bus operation | John Steven Dodson, Derek E. Williams, Jerry Don Lewis | 2001-01-16 |
| 6173371 | Demand-based issuance of cache operations to a processor bus | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 2001-01-09 |
| 6161189 | Latch-and-hold circuit that permits subcircuits of an integrated circuit to operate at different frequencies | Jerry Don Lewis, Derek E. Williams | 2000-12-12 |
| 6157980 | Cache directory addressing scheme for variable cache sizes | John Steven Dodson, Jerry Don Lewis | 2000-12-05 |
| 6145057 | Precise method and system for selecting an alternative cache entry for replacement in response to a conflict between cache operation requests | John Steven Dodson | 2000-11-07 |
| 6145038 | Method and system for early slave forwarding of strictly ordered bus operations | Jerry Don Lewis, John Steven Dodson | 2000-11-07 |
| 6145059 | Cache coherency protocols with posted operations and tagged coherency states | John Steven Dodson, Jerry Don Lewis | 2000-11-07 |
| 6141733 | Cache coherency protocol with independent implementation of optimized cache operations | John Steven Dodson, Jerry Don Lewis | 2000-10-31 |
| 6141714 | Method and apparatus for executing self-snooped unresolvable system bus operations | Derek E. Williams, John Michael Kaiser | 2000-10-31 |
| 6138218 | Forward progress on retried snoop hits by altering the coherency state of a local cache | John Steven Dodson, Jerry Don Lewis | 2000-10-24 |
| 6128707 | Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles | John Steven Dodson, Jerry Don Lewis | 2000-10-03 |
| 6128705 | Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations | John Michael Kaiser, Derek E. Williams | 2000-10-03 |