Issued Patents All Time
Showing 426–450 of 508 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6122691 | Apparatus and method of layering cache and architectural specific functions to permit generic interface definition | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 2000-09-19 |
| 6115794 | Method and system of providing a pseudo-precise inclusivity scheme in a sectored cache memory for maintaining cache coherency within a data-processing system | John Steven Dodson | 2000-09-05 |
| 6112270 | Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system | Jerry Don Lewis, John Steven Dodson | 2000-08-29 |
| 6105112 | Dynamic folding of cache operations for multiple coherency-size systems | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 2000-08-15 |
| 6101582 | Dcbst with icbi mechanism | John Steven Dodson, Jerry Don Lewis | 2000-08-08 |
| 6094710 | Method and system for increasing system memory bandwidth within a symmetric multiprocessor data-processing system | John Steven Dodson, Jerry Don Lewis | 2000-07-25 |
| 6092132 | Method and apparatus for monitoring 60x bus signals at a reduced frequency | Keenan W. Franz, David B. Shuler, Derek E. Williams | 2000-07-18 |
| 6085288 | Dual cache directories with respective queue independently executing its content and allowing staggered write operations | John Steven Dodson, Jerry Don Lewis, Timothy M. Skergan | 2000-07-04 |
| 6078991 | Method and system for speculatively requesting system data bus for sourcing cache memory data within a multiprocessor data-processing system | John Steven Dodson, Jerry Don Lewis | 2000-06-20 |
| 6065086 | Demand based sync bus operation | John Steven Dodson, Derek E. Williams, Jerry Don Lewis | 2000-05-16 |
| 6061755 | Method of layering cache and architectural specific functions to promote operation symmetry | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 2000-05-09 |
| 6061757 | Handling interrupts by returning and requeuing currently executing interrupts for later resubmission when the currently executing interrupts are of lower priority than newly generated pending interrupts | John Michael Kaiser, Warren E. Maule | 2000-05-09 |
| 6061762 | Apparatus and method for separately layering cache and architectural specific functions in different operational controllers | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 2000-05-09 |
| 6058456 | Software-managed programmable unified/split caching mechanism for instructions and data | Leo James Clark, John Steven Dodson, Jerry Don Lewis | 2000-05-02 |
| 6055608 | Method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system | John Steven Dodson, Jerry Don Lewis | 2000-04-25 |
| 6052762 | Method and apparatus for reducing system snoop latency | John Michael Kaiser, Warren E. Maule | 2000-04-18 |
| 6049849 | Imprecise method and system for selecting an alternative cache entry for replacement in response to a conflict between cache operation requests | John Steven Dodson | 2000-04-11 |
| 6038642 | Method and system for assigning cache memory utilization within a symmetric multiprocessor data-processing system | John Steven Dodson, Jerry Don Lewis | 2000-03-14 |
| 6032226 | Method and apparatus for layering cache and architectural specific functions to expedite multiple design | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 2000-02-29 |
| 6029204 | Precise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retries | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 2000-02-22 |
| 6029217 | Queued arbitration mechanism for data processing system | John Michael Kaiser | 2000-02-22 |
| 6026470 | Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels | Leo James Clark, John Steven Dodson, Jerry Don Lewis | 2000-02-15 |
| 6023746 | Dual associative-cache directories allowing simultaneous read operation using two buses with multiplexors, address tags, memory block control signals, single clock cycle operation and error correction | John Steven Dodson, Jerry Don Lewis, Timothy M. Skergan | 2000-02-08 |
| 6021468 | Cache coherency protocol with efficient write-through aliasing | John Steven Dodson, Jerry Don Lewis | 2000-02-01 |
| 6018791 | Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states | John Steven Dodson, Jerry Don Lewis | 2000-01-25 |