Issued Patents All Time
Showing 476–500 of 508 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5931924 | Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 1999-08-03 |
| 5924118 | Method and system for speculatively sourcing cache memory data prior to upstream cache invalidation within a multiprocessor data-processing system | John Steven Dodson, Jerry Don Lewis | 1999-07-13 |
| 5924121 | Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles | John Steven Dodson, Jerry Don Lewis | 1999-07-13 |
| 5913231 | Method and system for high speed memory address forwarding mechanism | Jerry Don Lewis, John Steven Dodson | 1999-06-15 |
| 5909561 | Apparatus and method for separately layering cache and architectural specific functions in different operational controllers to facilitate design extension | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 1999-06-01 |
| 5909698 | Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory | John Steven Dodson, Jerry Don Lewis | 1999-06-01 |
| 5901299 | Method and apparatus for transferring data between buses having differing ordering policies | Derek E. Williams | 1999-05-04 |
| 5896539 | Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determined weighted pseudo-random priorities | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 1999-04-20 |
| 5895495 | Demand-based larx-reserve protocol for SMP system buses | John Steven Dodson, Jerry Don Lewis, Derek E. Williams | 1999-04-20 |
| 5895484 | Method and system for speculatively accessing cache memory data within a multiprocessor data-processing system using a cache controller | John Steven Dodson, Jerry Don Lewis | 1999-04-20 |
| 5894569 | Method and system for back-end gathering of store instructions within a data-processing system | John Steven Dodson, Jerry Don Lewis | 1999-04-13 |
| 5893163 | Method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system | John Steven Dodson, Jerry Don Lewis | 1999-04-06 |
| 5883904 | Method for recoverability via redundant cache arrays | John Steven Dodson, Jerry Don Lewis, Timothy M. Skergan | 1999-03-16 |
| 5867511 | Method for high-speed recoverable directory access | John Steven Dodson, Jerry Don Lewis, Timothy M. Skergan | 1999-02-02 |
| 5860101 | Scalable symmetric multiprocessor data-processing system with data allocation among private caches and segments of system memory | John Steven Dodson, Jerry Don Lewis | 1999-01-12 |
| 5796979 | Data processing system having demand based write through cache with enforced ordering | John Steven Dodson, Guy L. Guthrie, Jerry Don Lewis | 1998-08-18 |
| 5790625 | Mechanism for enabling an array of numerous large high speed counters | — | 1998-08-04 |
| 5771247 | Low latency error reporting for high performance bus | Michael S. Allen, John Michael Kaiser, William Kurt Lewchuk | 1998-06-23 |
| 5745698 | System and method for communicating between devices | Michael S. Allen, John Michael Kaiser, William Kurt Lewchuk | 1998-04-28 |
| 5687327 | System and method for allocating bus resources in a data processing system | John Michael Kaiser, William Kurt Lewchuk, Michael S. Allen | 1997-11-11 |
| 5671370 | Alternating data valid control signals for high performance data transfer | Michael S. Allen, John Michael Kaiser, William Kurt Lewchuk | 1997-09-23 |
| 5659708 | Cache coherency in a multiprocessing system | John Michael Kaiser, William Kurt Lewchuk, Michael S. Allen | 1997-08-19 |
| 5623694 | Aborting an I/O operation started before all system data is received by the I/O controller after detecting a remote retry operation | John Steven Dodson, Jerry Don Lewis | 1997-04-22 |
| 5613153 | Coherency and synchronization mechanisms for I/O channel controllers in a data processing system | John Steven Dodson, Guy L. Guthrie, Jerry Don Lewis | 1997-03-18 |
| 5608878 | Dual latency status and coherency reporting for a multiprocessing system | John Michael Kaiser, William Kurt Lewchuk, Michael S. Allen | 1997-03-04 |