Issued Patents All Time
Showing 251–275 of 508 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6629268 | Method and apparatus for servicing a processing system through a test port | Kevin F. Reick | 2003-09-30 |
| 6629214 | Extended cache coherency protocol with a persistent “lock acquired” state | Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6629212 | High speed lock acquisition mechanism with time parameterized cache coherency states | Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6629210 | Intelligent cache management mechanism via processor access sequence analysis | John Steven Dodson, James Stephen Fields, Jr., Guy L. Guthrie | 2003-09-30 |
| 6629209 | Cache coherency protocol permitting sharing of a locked data granule | Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6625660 | Multiprocessor speculation mechanism for efficiently managing multiple barrier operations | Guy L. Guthrie, John Steven Dodson, Derek E. Williams | 2003-09-23 |
| 6625701 | Extended cache coherency protocol with a modified store instruction lock release indicator | Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-09-23 |
| 6622222 | Sequencing data on a shared data bus via a memory buffer to prevent data overlap during multiple memory read operations | James Stephen Fields, Jr., Warren E. Maule | 2003-09-16 |
| 6615322 | Two-stage request protocol for accessing remote memory data in a NUMA data processing system | John Steven Dodson, James Stephen Fields, Jr. | 2003-09-02 |
| 6615320 | Store collapsing mechanism for SMP computer system | John Steven Dodson, Guy L. Guthrie | 2003-09-02 |
| 6615321 | Mechanism for collapsing store misses in an SMP computer system | John Steven Dodson, Guy L. Guthrie | 2003-09-02 |
| 6609192 | System and method for asynchronously overlapping storage barrier operations with old and new storage operations | Guy L. Guthrie, John Steven Dodson, Derek E. Williams | 2003-08-19 |
| 6606680 | Method and apparatus for accessing banked embedded dynamic random access memory devices | James Stephen Fields, Jr., Sanjeev Ghai, Praveen S. Reddy, William J. Starke | 2003-08-12 |
| 6606702 | Multiprocessor speculation mechanism with imprecise recycling of storage operations | Guy L. Guthrie, John Steven Dodson, Derek E. Williams | 2003-08-12 |
| 6601145 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls | James Stephen Fields, Jr., Sanjeev Ghai, Guy L. Guthrie, Jody B. Joyner | 2003-07-29 |
| 6601144 | Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis | John Steven Dodson, James Stephen Fields, Jr., Guy L. Guthrie | 2003-07-29 |
| 6598118 | Data processing system with HSA (hashed storage architecture) | Leo James Clark, John S. Dodson, Guy L. Guthrie, Jerry Don Lewis | 2003-07-22 |
| 6591307 | Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response | James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2003-07-08 |
| 6591321 | Multiprocessor system bus protocol with group addresses, responses, and priorities | James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2003-07-08 |
| 6587926 | Incremental tag build for hierarchical memory architecture | John Steven Dodson, Jerry Don Lewis | 2003-07-01 |
| 6587924 | Scarfing within a hierarchical memory architecture | John Steven Dodson, Jerry Don Lewis | 2003-07-01 |
| 6587925 | Elimination of vertical bus queueing within a hierarchical memory architecture | John Steven Dodson, Jerry Don Lewis | 2003-07-01 |
| 6581115 | Data processing system with configurable memory bus and scalability ports | Lakshminarayana B. Arimilli, Leo James Clark, James S. Fields, Jr. | 2003-06-17 |
| 6581116 | Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system | Vicente Enrique Chung, Warren E. Maule | 2003-06-17 |
| 6581139 | Set-associative cache memory having asymmetric latency among sets | Lakshminarayana B. Arimilli, John Steven Dodson, James Stephen Fields, Jr., Guy L. Guthrie | 2003-06-17 |