Issued Patents All Time
Showing 476–500 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9690583 | Exploiting an architected list-use operand indication in a computer system operand resource pool | Valentina Salapura | 2017-06-27 |
| 9690623 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Eric M. Schwarz, Chung-Lung K. Shum | 2017-06-27 |
| 9690589 | Computer instructions for activating and deactivating operands | Valentina Salapura | 2017-06-27 |
| 9690509 | Computer instructions for limiting access violation reporting when accessing strings and similar data structures | Brett Olsson, Raul E. Silvera | 2017-06-27 |
| 9690556 | Code optimization to enable and disable coalescing of memory transactions | Fadi Y. Busaba, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2017-06-27 |
| 9684599 | Hybrid tracking of transaction read and write sets | Valentina Salapura, Chung-Lung K. Shum | 2017-06-20 |
| 9684537 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Eric M. Schwarz, Chung-Lung K. Shum | 2017-06-20 |
| 9678886 | Processing page fault exceptions in supervisory software when accessing strings and similar data structures using normal load instructions | Brett Olsson | 2017-06-13 |
| 9678757 | Forming instruction groups based on decode time instruction optimization | — | 2017-06-13 |
| 9678756 | Forming instruction groups based on decode time instruction optimization | — | 2017-06-13 |
| 9665500 | System supporting multiple partitions with differing translation formats | — | 2017-05-30 |
| 9665499 | System supporting multiple partitions with differing translation formats | — | 2017-05-30 |
| 9658961 | Speculation control for improving transaction success rate, and instruction therefor | Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2017-05-23 |
| 9658821 | Single operation array index computation | — | 2017-05-23 |
| 9652231 | All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture | Alexandre E. Eichenberger, Bruce M. Fleischer | 2017-05-16 |
| 9645879 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2017-05-09 |
| 9639415 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2017-05-02 |
| 9639370 | Software instructed dynamic branch history pattern adjustment | Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2017-05-02 |
| 9632819 | Collecting memory operand access characteristics during transactional execution | Dan F. Greiner, Valentina Salapura, Timothy J. Slegel | 2017-04-25 |
| 9632820 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2017-04-25 |
| 9626188 | Relative offset branching in a fixed-width reduced instruction set computing architecture | — | 2017-04-18 |
| 9628323 | Selective routing of asynchronous event notifications | Giles R. Frazier | 2017-04-18 |
| 9626168 | Compiler optimizations for vector instructions | Jin Song Ji, Ronald I. McIntosh, Steven J. Munroe, William J. Schmidt | 2017-04-18 |
| 9619232 | Predictive fetching and decoding for selected instructions | Valentina Salapura | 2017-04-11 |
| 9619383 | Dynamic predictor for coalescing memory transactions | Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Eric M. Schwarz | 2017-04-11 |