Issued Patents All Time
Showing 501–525 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9619230 | Predictive fetching and decoding for selected instructions | Valentina Salapura | 2017-04-11 |
| 9619214 | Compiler optimizations for vector instructions | Jin Song Ji, Ronald I. McIntosh, Steven J. Munroe, William J. Schmidt | 2017-04-11 |
| 9606855 | Caller protected stack return address in a hardware managed stack architecture | Karl J. Duvalsaint, Valentina Salapura | 2017-03-28 |
| 9606804 | Absolute address branching in a fixed-width reduced instruction set computing architecture | — | 2017-03-28 |
| 9606780 | Compiler method for generating instructions for vector operations on a multi-endian processor | Jin Song Ji, William J. Schmidt | 2017-03-28 |
| 9600282 | Endian-mode-independent memory access in a bi-endian-mode processor architecture | Brett Olsson | 2017-03-21 |
| 9600419 | Selectable address translation mechanisms | Anthony J. Bybell, Bradly G. Frey | 2017-03-21 |
| 9600292 | Common boot sequence for control utility able to be initialized in multiple architectures | — | 2017-03-21 |
| 9600287 | Latent modification instruction for transactional execution | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2017-03-21 |
| 9600286 | Latent modification instruction for transactional execution | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2017-03-21 |
| 9600281 | Matrix multiplication operations using pair-wise load and splat operations | Alexandre E. Eichenberger, John A. Gunnels, Valentina Salapura | 2017-03-21 |
| 9600194 | Integrating sign extensions for loads | — | 2017-03-21 |
| 9594668 | Debugger display of vector register contents after compiler optimizations for vector instructions | William J. Schmidt | 2017-03-14 |
| 9594576 | Architectural mode configuration | Charles W. Gainey, Jr. | 2017-03-14 |
| 9588774 | Common boot sequence for control utility able to be initialized in multiple architectures | — | 2017-03-07 |
| 9588763 | Vector find element not equal instruction | Jonathan D. Bradbury, Eric M. Schwarz, Timothy J. Slegel | 2017-03-07 |
| 9588762 | Vector find element not equal instruction | Jonathan D. Bradbury, Eric M. Schwarz, Timothy J. Slegel | 2017-03-07 |
| 9588746 | Compiler method for generating instructions for vector operations on a multi-endian processor | Jin Song Ji, William J. Schmidt | 2017-03-07 |
| 9582424 | Counter-based wide fetch management | Jose E. Moreira | 2017-02-28 |
| 9582423 | Counter-based wide fetch management | Jose E. Moreira | 2017-02-28 |
| 9582413 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Christian Jacobi, Timothy J. Slegel | 2017-02-28 |
| 9582315 | Software enabled and disabled coalescing of memory transactions | Fadi Y. Busaba, Valentina Salapura, Chung-Lung K. Shum | 2017-02-28 |
| 9582295 | Architectural mode configuration | Charles W. Gainey, Jr. | 2017-02-28 |
| 9582279 | Execution of condition-based instructions | — | 2017-02-28 |
| 9582274 | Architected store and verify guard word instructions | — | 2017-02-28 |