Issued Patents All Time
Showing 26–50 of 105 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9653308 | Epitaxial lift-off process with guided etching | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Leathen Shi | 2017-05-16 |
| 9608160 | Polarization free gallium nitride-based photonic devices on nanopatterned silicon | Can Bayram, Cheng-Wei Cheng, Tayfun Gokmen, Ning Li, John A. Ott +1 more | 2017-03-28 |
| 9595805 | III-V photonic integrated circuits on silicon substrate | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana | 2017-03-14 |
| 9590393 | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana | 2017-03-07 |
| 9589791 | Compound finFET device including oxidized III-V fin isolator | Szu-Lin Cheng, Isaac Lauer, Jeng-Bang Yau | 2017-03-07 |
| 9570296 | Preparation of low defect density of III-V on Si for device fabrication | Cheng-Wei Cheng, Devendra K. Sadana, Yanning Sun | 2017-02-14 |
| 9564494 | Enhanced defect reduction for heteroepitaxy by seed shape engineering | Cheng-Wei Cheng, David L. Rath, Devendra K. Sadana, Brent A. Wacaser | 2017-02-07 |
| 9548355 | Compound finFET device including oxidized III-V fin isolator | Szu-Lin Cheng, Isaac Lauer, Jeng-Bang Yau | 2017-01-17 |
| 9508640 | Multiple via structure and method | Cheng-Wei Cheng, Szu-Lin Cheng, Keith E. Fogel, Edward W. Kiewra, Amlan Majumdar +2 more | 2016-11-29 |
| 9496347 | Graded buffer epitaxy in aspect ratio trapping | Cheng-Wei Cheng, Amlan Majumdar, Jeng-Bang Yau | 2016-11-15 |
| 9459797 | Uniformly distributed self-assembled cone-shaped pillars for high efficiency solar cells | Christos D. Dimitrakopoulos, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana | 2016-10-04 |
| 9431301 | Nanowire field effect transistor (FET) and method for fabricating the same | Jack O. Chu, Szu-Lin Cheng, Isaac Lauer, Jeng-Bang Yau | 2016-08-30 |
| 9412744 | III-V CMOS integration on silicon substrate via embedded germanium-containing layer | Cheng-Wei Cheng, Devendra K. Sadana | 2016-08-09 |
| 9407066 | III-V lasers with integrated silicon photonic circuits | Cheng-Wei Cheng, Frank R. Libsch, Tak H. Ning, Uzma Rana | 2016-08-02 |
| 9406530 | Techniques for fabricating reduced-line-edge-roughness trenches for aspect ratio trapping | Guy M. Cohen, Katherine L. Saenger | 2016-08-02 |
| 9406566 | Integration of III-V compound materials on silicon | Cheng-Wei Cheng, Sanghoon Lee | 2016-08-02 |
| 9401583 | Laser structure on silicon using aspect ratio trapping growth | Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana | 2016-07-26 |
| 9397226 | Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts | Anirban Basu, Cheng-Wei Cheng, Wilfried E. Haensch, Amlan Majumdar | 2016-07-19 |
| 9395489 | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana | 2016-07-19 |
| 9391144 | Selective gallium nitride regrowth on (100) silicon | Can Bayram, Cheng-Wei Cheng, Devendra K. Sadana | 2016-07-12 |
| 9368407 | Crack control for substrate separation | Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Katherine L. Saenger | 2016-06-14 |
| 9344200 | Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana | 2016-05-17 |
| 9337281 | Planar semiconductor growth on III-V material | Cheng-Wei Cheng, Jack O. Chu, Devendra K. Sadana, Yanning Sun | 2016-05-10 |
| 9324853 | III-V semiconductor device having self-aligned contacts | Anirban Basu, Amlan Majumdar, Yanning Sun | 2016-04-26 |
| 9318641 | Nanowires formed by employing solder nanodots | Keith E. Fogel, Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana | 2016-04-19 |